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In the recent years, development of various organic and inorganic nano-sized systems has gained great interests especially for cancer diagnosis and treatment and intense researches are carried out in this area. Regarding to the recent trends for drug delivery system design, the novel approaches for drug carriers are mainly based on development of smart and nano-size drug carriers which are targeted to cancer cells. Hence, for an effective tumor-targeted delivery device, besides its chemical structure further criteria such as detection of tumor site and sensitivity to the higher temperature and lower pH of the tumor compare to rest of the body gains importance. The aim of this study is to design and prepare polysebacic anhydride (PSA) based nanocapsules (NCs) loaded with Doxorubicin (DOX) which is an anti cancer drug. In order to obtain an intelligent delivery system, drug-loaded nanocapsules were coated with pH sensitive poly (L-histidine). PSA nano-carriers were firstly loaded with DOX and then in order to introduce pH sensitivity, they were coated with poly (L-histidine). PLH-coated NCs were modified with polyethylene glycol (PEG) to prevent their macrophage uptake. Drug release profile from this system was examined in two different buffer solutions prepared as acidic (pH 4) and physiological (pH 7.4) media. The physical and chemical properties of the nano particles were characterized by Fourier transform infrared spectroscopy (FTIR), dynamic light scattering (DLS), ultraviolet and visible absorption spectroscopy (UV-VIS), and scanning electron microscopy (SEM). In vitro studies of the prepared nanocapsules were performed on MDA-MB-231 breast cancer cells by using WST Kit 8 cell viability test. In order to obtained results, pH sensitive nanocapsules with size 230 nm exhibited cellular uptake and promising intracellular release of drug.

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field.<p> A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market.<p> Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. <p> The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. <p> A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation.<p> Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. <p> A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

GE Healthcare operates in Uppsala (Sweden) and develops systems, equipments and medium to purify medical substances. Discussions with the local authority concerning planed far-reaching changes and upgrades of the biological process techniques for sewage management, aroused the question about revising the terms of permit for the activity. Therefore it seemed necessary to evaluate a newly installed biological process technique, which is the background of this thesis. The evaluated biological treatment process was built in 2003 and consists of a biological reactor filled with moving bed carriers with a high surface area for biological growth. At the time of the project the biological wastewater treatment plant consisted of a flow equalization facility and two following parallel biological processes; a biological reactor with moving bed carriers and a tower trickling filter. The aim of this thesis was to survey the function of the biological reactor with respect to the reduction of organic matter. Further to clarify which circumstances that have a negative effect on the organic reduction. During the three forthcoming years, an extensive reconstruction of the biological wastewater treatment facility will be accomplished. During the construction period the flow equalization will be very limited. Therefore an emission forecast with respect to organic matter was performed comprising the construction period during the years 2005, 2006 and 2007. This to estimate the safety margin to the emission standard during the construction period. Several parameters were surveyed during the project, water temperature, pH, plural nutrition elements, flow, oxygen concentration, suspended solids, organic load and microbial activity. At two occasions, the parameters were extensively studied during a 24-hour period respectively. Two capacity experiments were performed in order to evaluate the organic reduction at different organic loads. The obtained results together with an estimation regarding the organic load performed by AB Ångpanneföreningen were used for the emission forecast. The forecast considered two cases, operation with and without dosage of a flow with high organic content from the local solvent recycling facility (called T10-dosage). According to the forecast, the emission standard will be fulfilled during an average month regarding the organic load. This without T10-dosage and with an average reduction of 55 %. To fulfill the standard during a month with maximum organic load, a reduction of 65 and 75 % will be required in the cases without and with T10-dosage respectively. The organic reduction is negatively effected by lasting loads of 7 kg CODfilt/m3 or higher, or by a great increase of the load in a short period of time. Sporadic peaks regarding the organic load appeared to have temporary or no negative effects on the reduction. Flow variations during evenings, nights and weekends caused variations in the organic load with negative effect of the reduction rate. The oxygen concentration in the biological reactor has a conclusive significance of the reduction rate, a lower concentration than 2 mg/l affects the reduction rate in a negative way. The buffering capacity in the biofilm reactor showed to work excellently, the pH value varied between 6.8 and 8.9. There is an immediate risk of temperatures over 40oC during the construction period. This could have a negative influence of the organic reduction. Individual measured temperatures of 38oC did not have a negative effect on the reduction rate. The amount of suspended solids varied a lot in the outflow from the biological reactor and will continue to do so during the construction period. / GE Healthcare bedriver sin verksamhet i Uppsala vilken består av att utveckla system, utrustning och media för att rena läkemedelssubstanser. Vid diskussion med Uppsala kommuns VA- och avfallskontor väcktes frågan angående omprövning av tillståndet för verksamheten. Diskussionerna rörde planerade processförändringar och kompletteringar av bolagets biologiska processavloppsvattenrening. Av den anledningen ansågs det nödvändigt att utreda en för företaget ny processteknik för processavloppsvatten, vilket är bakgrunden till detta examensarbete. Den utvärderade processtekniken är en biofilmreaktor innehållande ett rörligt bärarmaterial med en stor skyddad yta för biologisk tillväxt. Biofilmreaktorn togs i drift under hösten år 2003 och därmed bestod det lokala reningsverket förenklat sett av en utjämningsanläggning följd av två parallella biosteg, ett biotorn med konventionell stationär biobädd över vilken processavloppsvatten spreds samt en biofilmreaktor med rörligt bärarmaterial. Syftet med examensarbetet var att kartlägga biofilmreaktorns funktion med avseende på reduktion av organiskt material. Vidare att klargöra vid vilka förhållanden reduktionsgraden har påverkats negativt. Under de tre kommande åren skall en stor om- och tillbyggnad av reningsverket genomföras. Förändringen kommer att medföra att utjämningsvolymen blir mycket begränsad under ombyggnadsperioden. Av den anledningen var ytterligare ett syfte med examensarbetet att utföra en utsläppsprognos med avseende på organiskt material för åren 2005 till och med 2007. Detta för att bedöma säkerhetsmarginalen till utsläppsvillkoret under ombyggnadsperioden. Examensarbetet realiserades genom att kartlägga parametrarna organisk belastning, organisk reduktion, vattentemperatur, pH, närsalter, flöde, koncentration löst syre, suspenderad substans samt mikrobiell aktivitet. Därutöver utfördes två kapacitetsförsök för att kartlägga den organiska belastningens inverkan på reduktionen. Vid det ena försöket skapades en högre organisk belastning genom att successivt öka flödesbelastningen över biofilmreaktorn. Vid det andra försöket doserades en delström (kallad T10-dosering) innehållande rester från den lokala lösningsmedelsåtervinningen med stort organiskt innehåll. Därtill utfördes två dygnsprovtagningar för att kartlägga ett flertal parametrars dygnsvariationer. Den framtagna utsläppsprognosen baserades på en belastningsprognos utförd av AB Ångpanneföreningen samt den i arbetet kartlagda reduktionen av organiskt material vid olika belastningar. Prognosen omfattar två fall, med eller utan T10-dosering. Enligt utsläppsprognosen kommer utsläppsvillkoret inte att överskridas under åren 2005 till och med 2007. Detta gäller vid en för året genomsnittlig månad avseende belastning utan T10-dosering och med en genomsnittlig organisk reduktionsgrad på 55 %. Under en månad med maximal belastning krävs 65 % reduktion och 75 % med T10-dosering. Kapacitetsförsöken visade att reduktionsgraden påverkades negativt vid en varaktig belastning överstigande 7 kg CODlöst/m3 samt vid kraftiga belastningsökningar. Tillfälliga belastningstoppar hade endast kortvarig eller ingen negativ inverkan på reduktionen. Höga flöden under dagtid och låga flöden under nätter och helger orsakade variationer i den organiska belastningen, vilket hade en negativ inverkan på reduktionen. När koncentrationen löst syre i biofilmreaktorn understeg 2 mg/l påverkades mikroorganismerna negativt och därmed även reduktionen. Buffertkapaciteten i biofilmreaktorn var god under den studerade tidsperioden och pH-värdet varierade mellan 6,5 och 8,8. Under ombyggnadsperioden föreligger en stor risk för att vattentemperaturen kan bli för hög i biofilmreaktorn vid ett flertal tillfällen. Enstaka uppmätta temperaturtoppar på 38°C påverkade dock inte reduktionen negativt. I biofilmreaktorns utgående vatten varierade mängden suspenderad substans kraftigt, vilket även kommer att gälla under ombyggnadsperioden.

No description available.

The purpose of this thesis is to demonstrate the effects of mismatch errors that occur in time-interleaved analog-to-digital converters (TI-ADC) and how these are compensated for by proprietary methods from Signal Processing Devices Sweden AB. This will be demonstrated by two different implementations, both based on the combined digitizer/generator SDR14. These demonstrations shall be done in a way that is easy to grasp for people with limited knowledge in signal processing. The first implementation is an analog video demo where an analog video signal is sampled by such an TI-ADC in the SDR14, and then converted back to analog and displayed with the help of a TV tuner. The mismatch compensation can be turned on and off and the difference on the resulting video image is clearly visible. The second implementation is a digital communication demo based on W-CDMA, implemented on the FPGA of the SDR14. Four parallel W-CDMA signals of 5 MHz are sent and received by the SDR14. QPSK, 16-QAM, and 64-QAM modulated signals were successfully sent and the mismatch effects were clearly visible in the constellation diagrams. Techniques used are, for example: root-raised cosine pulse shaping, RF modulation, carrier recovery, and timing recovery.

This master’s thesis deals with studies of lateral and vertical carrier transport Dot-in- a-Well (DWELL) Quantum Dot Infrared Photodetectors (QDIPs). During the pro ject, devices have been developed and tested using a Fourier Transform Infrared (FTIR) spec- trometer with the purpose to find the processes governing the flow of photocurrent in the different kinds of detectors, the dark current magnitude in the vertical Quantum Dot Infrared Photodetector (QDIP) and the Quantum Well Infrared Photodetector (QWIP) and the light polarization dependences for the vertical QDIP and the QWIP. The lateral carrier transport DWELL QDIP was found to have poor conduction in the well mainly due to re-trapping of electrons in this region. The main process gov- erning the flow of photocurrent for this type of device at 77K is photo-excitation from the Quantum Dot (QD)s to the excited state in the Quantum Well (QW) and further thermal excitation. If the electrons are mainly transported in the matrix or the well at 77K is presently not clear. For the vertical carrier transport DWELL QDIP at 77K, the wavelength response could be tuned by altering the applied voltage. At higher voltages, the dominant process was found to be photo-excitation from the QDs to the excited state in the QW followed by thermal assisted tunneling into the GaAs-matrix. At lower voltages, photo-excitation from the QDs directly into the the GaAs-matrix was the predominant process. The dark current level in the vertical QDIPs was found to be 1.5 to 5 orders of magnitude smaller than for the QWIP measured at 77K. Furthermore, the QDIP was found to be close to polarization independent. As expected the QWIP had a reduced sensitivity to normal incident light. The existence of this signal was attributed to interface scattering of light inside the device.

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field.<p> A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market.<p> Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. <p> The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. <p> A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation.<p> Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. <p> A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection.