Thesis (M. App. Sc.)--Carleton University, 2002. / Includes bibliographical references (p. 103-106). Also available in electronic format on the Internet.

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 79-82). Also available on the World Wide Web.

High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.

Ko, Chi Tung. / On t.p. "delta" and "sigma" appear as the Greek letters. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.1 / 摘要 --- p.3 / Acknowledgements --- p.4 / Table of Contents --- p.5 / List of Figures --- p.8 / List of Tables --- p.13 / Chapter Chapter 1 --- Introduction --- p.14 / Chapter 1.1 --- Motivation --- p.14 / Chapter 1.2 --- Objectives --- p.17 / Chapter 1.3 --- Organization of the Thesis --- p.17 / References --- p.18 / Chapter Chapter 2 --- Fundamentals of Delta-sigma Modulators --- p.20 / Chapter 2.1 --- Delta-sigma Modulator as a Feedback System --- p.20 / Chapter 2.2 --- Quantization Noise --- p.22 / Chapter 2.3 --- Oversampling --- p.23 / Chapter 2.4 --- Noise Shaping --- p.25 / Chapter 2.5 --- Performance Parameters --- p.27 / Chapter 2.6 --- Baseband Modulators vs Bandpass Modulators --- p.27 / Chapter 2.7 --- Discrete-time Modulators vs Continuous-time Modulators --- p.28 / Chapter 2.8 --- Single-bit Modulators vs Multi-bit Modulators --- p.29 / Chapter 2.9 --- Non-linearity and Image Problems in Multi-bit Delta-sigma Modulators --- p.29 / Chapter 2.9.1 --- Non-linearity Problem --- p.29 / Chapter 2.9.2 --- Image Problem --- p.31 / Reference --- p.36 / Chapter Chapter 3 --- Image Rejection and Non-linearity Suppression Techniques for Quadrature Multi-bit Δ¡♭ Modulators --- p.38 / Chapter 3.1 --- Quadrature DEM Technique --- p.38 / Chapter 3.1.1 --- Introduction and Working Principle --- p.38 / Chapter 3.1.2 --- Behavioral Simulation Results --- p.42 / Chapter 3.2 --- IQ DWA Technique --- p.44 / Chapter 3.2.1 --- Introduction and Working Principle --- p.44 / Chapter 3.2.2 --- Behavioral Simulation Results --- p.49 / Chapter 3.3 --- DWA and Bit-wise Data-Dependent DEM --- p.52 / Chapter 3.3.1 --- Introduction and Working Principle --- p.52 / Chapter 3.3.2 --- Behavioral Simulation Results --- p.54 / Chapter 3.4 --- Image Rejection Technique for Quadrature Mixer --- p.61 / Chapter 3.5 --- Conclusion --- p.63 / Reference --- p.64 / Chapter Chapter 4 --- System Design of a Multi-Bit CT Modulator for GSM/WCDMA Application --- p.65 / Chapter 4.1 --- Objective of Design and Design Specification --- p.65 / Chapter 4.2 --- Topology Selection --- p.65 / Chapter 4.3 --- Discrete-time Noise Transfer Function Generation --- p.66 / Chapter 4.4 --- Continuous-time Loop Filter Transfer Function Generation --- p.69 / Chapter 4.5 --- Behavioral Model of Modulator --- p.69 / Chapter 4.6 --- Dynamic Range Scaling --- p.75 / Chapter 4.7 --- Behavioral Modeling of Operational Amplifiers --- p.77 / Chapter 4.8 --- Impact of RC Variation on Performance --- p.85 / Chapter 4.9 --- Loop Filter Component Values --- p.88 / Chapter 4.10 --- Summary --- p.90 / Reference --- p.90 / Chapter Chapter 5 --- Transistor-level Implementation of Modulators --- p.92 / Chapter 5.1 --- Overview of Design --- p.92 / Chapter 5.2 --- Design of Operational Transconductance Amplifiers (OTAs) --- p.94 / Chapter 5.2.1 --- First Stage --- p.94 / Chapter 5.2.2 --- Second and Third Stages --- p.98 / Chapter 5.3 --- Design of Feed-forward Transconductance (Gm) Cells --- p.101 / Chapter 5.4 --- Design of Quantizer --- p.102 / Chapter 5.4.1 --- Reference Ladder Design --- p.102 / Chapter 5.4.2 --- Comparator Design --- p.104 / Chapter 5.5 --- Design of Feedback Digital-to-Analog Converter (DAC) --- p.106 / Chapter 5.5.1 --- DWA and DEM Logic --- p.107 / Chapter 5.5.2 --- DAC Circuit --- p.109 / Chapter 5.6 --- Design of Integrated Mixers --- p.111 / Chapter 5.7 --- Design of Clock Generators --- p.112 / Chapter 5.7.1 --- Master Clock Generator --- p.112 / Chapter 5.7.2 --- LO Clock Generator --- p.114 / Chapter 5.7.3 --- Simulation Results --- p.116 / Reference --- p.125 / Chapter Chapter 6 --- Physical Design of Modulators --- p.127 / Chapter 6.1 --- Floor Planning of Modulator --- p.127 / Chapter 6.2 --- Shielding of Sensitive Signals --- p.130 / Chapter 6.3 --- Common Centroid Layout --- p.130 / Chapter 6.4 --- Amplifier Layout --- p.132 / Reference --- p.137 / Chapter Chapter 7 --- Conclusions --- p.138 / Chapter 7.1 --- Conclusions --- p.138 / Chapter 7.2 --- Future Works --- p.138 / Appendix A Schematics of Building Blocks --- p.140 / First Stage Operational Amplifier --- p.140 / First Stage Amplifier Local Bias Circuit --- p.140 / Second and Third Stage Operational Amplifier --- p.141 / Second and Third Stage Local Bias Circuit --- p.141 / CMFB Circuit (First Stage) --- p.142 / CMFB Circuit (Second Stage) --- p.142 / Gm-Feed-forward Cells --- p.143 / Gm Feed-forward Cell Bias Circuit --- p.143 / Reference Ladder Circuit --- p.144 / Pre-amplifier Circuit --- p.145 / Latch Circuit --- p.145 / DAC Circuit (Unit Cell) --- p.146 / Author's Publications --- p.147

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.

Η παρούσα Διπλωματική Εργασία εστίασε το ενδιαφέρον της στην διερεύνηση των μοντέλων για νευρώνες (neuron models) ικανών να μιμηθούν την φυσική λειτουργία των βιολογικών νευρώνων. Συγκεκριμένα, έγινε μελέτη κάποιων μοντέλων για νευρώνες που παρουσιαστήκαν τα τελευταία χρόνια και στην συνέχεια, σχεδιάστηκε και υλοποιήθηκε ένα από τα μοντέλα αυτά κάνοντας χρήση κυκλωμάτων χαμηλής τάσης τροφοδοσίας στο πεδίο του υπερβολικού ημιτόνου (Sinh-Domain). Η γρήγορη ανάπτυξη της μικροηλεκτρονικής στην υλοποίηση συστημάτων υψηλής αξιοπιστίας και απόδοσης μικρού βάρους και όγκου όπως φορητών ηλεκτρονικών πολυμέσων, επικοινωνιών, βιοϊατρικών συσκευών, ωθεί στην σχεδίαση των ολοκληρωμένων κυκλωμάτων που τα απαρτίζουν με μειωμένη κατανάλωση ισχύος και κατ’ επέκταση χαμηλής τάσης τροφοδοσίας. Αρχικά, γίνεται μια εισαγωγή για τη σχεδίαση ολοκληρωμένων κυκλωμάτων για λειτουργία σε περιβάλλον χαμηλής τάσης τροφοδοσίας. Ακολούθως, δίνεται η περιγραφή της δομής και της λειτουργίας ενός βιολογικού νευρώνα και στην συνέχεια η περιγραφή των δύο βασικών μοντέλων νευρώνα (neuron models) που μελετήθηκαν στα πλαίσια της συγκεκριμένης εργασίας. Επίσης, παρουσιάζεται μία πρόσφατη υλοποίηση του βασικού μοντέλου νευρώνα των Mihalas και Niebur που ερευνάται στα πλαίσια της παρούσας εργασίας, στο πεδίο του λογαρίθμου καθώς και τα μοτίβα αιχμών τα οποία είναι ικανό να παράγει το συγκεκριμένο μοντέλο στο πεδίο του λογαρίθμου. Τον πυρήνα στην σχεδίαση των συγκεκριμένων μοντέλων για νευρώνες που μελετώνται, αποτελεί η τοπολογία του Tau-Cell. Η συγκεκριμένη βαθμίδα χρησιμοποιείται για την συστηματική σχεδίαση φίλτρων στο πεδίο του λογαρίθμου (Log-Domain filters). Έπειτα, αναλύεται η μέθοδος σχεδίασης κυκλωμάτων, και συγκεκριμένα φίλτρων, χαμηλής τάσης τροφοδοσίας στο πεδίο του υπερβολικού ημιτόνου (Sinh-Domain). Παρουσιάζονται οι βασικούς τελεστές καθώς και τα βασικά cells, για την σχεδίαση κυκλωμάτων στο πεδίο του υπερβολικού ημιτόνου (Sinh-Domain). Στην συνέχεια, περιγράφεται η σχεδίαση της τοπολογίας του Tau-Cell η οποία όπως αναφέραμε, αποτελεί τον πυρήνα στην υλοποίηση μοντέλων για νευρώνες, στο πεδίο του υπερβολικού ημιτόνου και επιβεβαιώνεται η ορθή λειτουργία της συγκεκριμένης βαθμίδας, με την σχεδίαση και εξομοίωση φίλτρων στο πεδίο του υπερβολικού ημιτόνου, με βασικό στοιχείο το Tau-Cell στο Analog Design Environment του λογισμικού της Cadence σε τεχνολογία της AMS CMOS 0.35μm. Αφότου έχει ολοκληρωθεί η σχεδίαση του Tau-Cell στο πεδίο του υπερβολικού ημιτόνου, περιγράφεται στην συνέχεια η υλοποίηση του μοντέλου νευρώνα των Mihalas και Niebur στο πεδίο του υπερβολικού ημιτόνου. Κάνοντας χρήση της βαθμίδας του Tau-Cell στο πεδίο του υπερβολικού ημιτόνου, γίνεται η υλοποίηση και στην συνέχεια η εξομοίωση, δύο βασικών κυκλωμάτων του μοντέλου, με βάση την ήδη υπάρχουσα υλοποίηση τους στο πεδίο του λογαρίθμου, ικανών να παράγουν διάφορα μοτίβα αιχμών (spiking patterns) με βάση το συγκεκριμένο μοντέλο του νευρώνα. Η ορθή λειτουργία των δύο αυτών κυκλωμάτων του μοντέλου με βάση τα μοτίβα αιχμών (spiking patterns) που είναι ικανά να παράγουν, επιβεβαιώνεται από τις εξομοιώσεις στο περιβάλλον του Analog Design Environment του λογισμικού της Cadence σε τεχνολογία της AMS CMOS 0.35μm. Τέλος, παρουσιάζεται η φυσική σχεδίαση (layout) των δύο βασικών κυκλωμάτων του μοντέλου νευρώνα καθώς και τα αποτελέσματα από την post-layout εξομοίωση του μοντέλου. Η φυσική σχεδίαση πραγματοποιήθηκε μέσω του λογισμικού Cadence το οποίο και περιέχει το περιβάλλον φυσικής σχεδίασης αναλογικών ηλεκτρονικών κυκλωμάτων Virtuoso Layout Editor. Η τεχνολογία που χρησιμοποιήθηκε αναφέρεται ως AMS C35D4 CMOS διαστάσεων 0.35μm. / This present M.Sc. Thesis is focused its interest in the study of neuron models that emulate the physical behavior of biological neurons. More specifically, we present a study of some neuron models that have been presented the last years and we proceed with the design and the implementation one of them using low voltage circuits in the Sinh-Domain. Τhe radical technological developments of microelectronics in the systems implementation with high reliability and performance, such as portable electronic devices for multimedia, communications and biomedical systems, demand the design of integrated circuits with reduced power consumption and thus low voltage supply. Initially, an introduction for the design of integrated circuits in low voltage environment is given and, also, the description of the structure and behavior of a biological neuron. Next, an analysis of two recently introduced neuron models realized in the Log-Domain, from which the Mihalas and Niebur neuron model constitutes the basic model studied in the context of this work and, also, the basic spiking patterns, that this implementation of the Mihalas-Niebur neuron model is capable of producing. The core in the implementation of this neuron models, is the topology of Tau-Cell. The topology of Tau-Cell is used for the systematic design of filters in the Log-Domain. Thereafter, is given an analysis of the method of designing low voltage circuits and more specifically filters, in the Sinh-Domain. The basic operators and the principal cells, for designing circuits in the Sinh-Domain are presented. Then, the design and implementation of the Tau-Cell topology which as mentioned is the core for the implementation of neuron models, is realized in the Sinh-Domain. The proper operation of this topology is confirmed through the design and simulation of filters in the Sinh-Domain, in the Analog Design Environment of Cadence using the AMS CMOS 0.35μm technology. After the design of the Tau-Cell in the Sinh-Domain, we continue with the implementation of the Mihalas-Niebur neuron model. Using the topology of Tau-Cell in the Sinh-Domain, we proceed with the implementation and the simulation of the basic two topologies of the neuron model based on the existing implementation in the Log-Domain. The implemented topologies of the neuron are capable of producing spiking patterns based to the Mihalas-Niebur neuron model. The proper operation of these topologies based on the spiking patterns that are capable of producing, is confirmed through the design and simulation in the Sinh-Domain, in the Analog Design Environment of Cadence using the AMS CMOS 0.35μm technology. Finally, is presented the layout design of the main two topologies of the neuron model and also the results of the post-layout simulations. The layout was conducted via the Cadence software through Virtuoso Layout Editor. The technology used is referred as AMS C35D4 CMOS in 0.35μm dimensions.

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected. / Graduation date: 2010