The oil and gas industry, aerospace, and automotive industries are constantly pushing technology beyond their current operational boundaries, spurring the need for extreme environment electronics. The oil and gas industry, in particular, is the oldest and largest market for high-temperature electronics, where the operating environment can extend up to 260 degrees Celsius. The electronics currently employed in this field are only rated to 200 degrees Celsius, but with the rise of wideband gap technologies, this could be extended to 250 degrees Celsius or more without the needed for active or passive cooling. This reduces the complexity, weight, and cost of the system while improving reliability. In addition, current downhole telemetry data rates are insufficient for supporting more sophisticated and higher resolution well-logging sensors. Increasing the data rates can also save the industry significant amount of time by decreasing the amount of well-logging excersions and by increasing the logging speed. Previous work done by this research group saw the prototyping of a high bit rate transceiver operating at 230 MHz - 300 MHz and 230 degrees Celsius; however, at these frequencies, the system could not meet size requirements. Thus, a new high-temperature high data rate transceiver design using the 2.4 GHz - 2.5 GHz ISM band is proposed to miniaturize the design and to allow for IC implementation. The transceiver was designed to meet the minimum specifications necessary to give designers flexibility between power consumption and performance. The performance of the design is simulated using AWR design environment software, which shows the system can support a downlink data rate up to 68 Mbps and an uplink data rate up to 170 Mbps across 10 channels. The effects temperature has on the system performance is also evaluated in the simulation. / Master of Science / The oil and gas industry is currently the largest and oldest market for high-temperature electronics. One of the major applications within this industry for high-temperature electronics is known as well-logging, during which a suite of sensors and systems is lowered into a well to survey the health and geology of the well. Among these sensors and systems, the communication system is one of the most crucial components as it relays real-time data back to the surface during the well-logging operation. Current high-temperature communication systems are capable of operating up to 200 ℃, meeting the operating requirements of current wells. As these wells deplete, however, new wells must be explored, and higher operating temperatures are expected. In addition, the communication systems currently employed fail to meet increasing data rate demands due to the growing complexity of the sensors. Recent developments in semiconductor technologies have given rise to devices, which can increase the operating temperature of electronics up to 250 ℃ while meeting demands for high data rate communication systems. Previous work has leveraged these devices to prototype such a system; however, the proof-of-concept failed to meet size and weight restrictions of practical systems. Therefore, a new system design for a high-temperature high data rate communication system is proposed. The system operates at 2.4 – 2.5 GHz to miniaturize the circuits and make chip implementation possible. The impacts of temperature on the system are investigated and the system performance is simulated within its intended operating temperature range. Developments from this research can be extended to the automotive and aerospace industries, where demand for high-temperature electronics is growing.

The interest in the development of wireless high-speed data services is in response to the strong market demand for high-speed wireless Internet access. Current standards aim at delivering a peak data rate greater than 2Mbps on the forward link. Since data services and voice services are fundamentally different, new concepts were introduced in the design of the forward data channel. In addition, methods of evaluating the performance of a cellular CDMA system have to be revisited. This thesis proposes a method which can be used to find the forward link peak and average data rates, throughput and coverage of a cellular CDMA system which is capable of delivering high-speed wireless data. A summary of changes in design philosophy and recent advances in technologies which enable high-speed wireless data delivery are presented. The proposed method takes into account major aspects commonly found in the forward data channel and applies the generalized Shannon capacity formula for multi-element antenna (MEA) systems. The analysis focuses on the physical layer and is flexible enough to be adapted to various propagation environments, antenna configurations, multicode allocations, user distributions and cell site configurations. Sample numerical results for various multicode allocations are shown using a system model with two-tier interfering cells with one transmit antenna and two receive antennas operating under a frequency selective slow fading channel with propagation environment described by the Recommendation ITU-R M. 1225 indoor office, outdoor to indoor and pedestrian and vehicular test environments. Different transmit / receive antenna configurations and multicode allocations and their impact on the average data rate is also explored.

The interest in the development of wireless high-speed data services is in response to the strong market demand for high-speed wireless Internet access. Current standards aim at delivering a peak data rate greater than 2Mbps on the forward link. Since data services and voice services are fundamentally different, new concepts were introduced in the design of the forward data channel. In addition, methods of evaluating the performance of a cellular CDMA system have to be revisited. This thesis proposes a method which can be used to find the forward link peak and average data rates, throughput and coverage of a cellular CDMA system which is capable of delivering high-speed wireless data. A summary of changes in design philosophy and recent advances in technologies which enable high-speed wireless data delivery are presented. The proposed method takes into account major aspects commonly found in the forward data channel and applies the generalized Shannon capacity formula for multi-element antenna (MEA) systems. The analysis focuses on the physical layer and is flexible enough to be adapted to various propagation environments, antenna configurations, multicode allocations, user distributions and cell site configurations. Sample numerical results for various multicode allocations are shown using a system model with two-tier interfering cells with one transmit antenna and two receive antennas operating under a frequency selective slow fading channel with propagation environment described by the Recommendation ITU-R M. 1225 indoor office, outdoor to indoor and pedestrian and vehicular test environments. Different transmit / receive antenna configurations and multicode allocations and their impact on the average data rate is also explored.

Ce travail porte sur l'étude de faisabilité d'une architecture radio, dédiée aux applications WPANs nomades et faible consommation en utilisant la bande autour de 60 GHz. Des débits de l'ordre de Gbps, une compacité élevée et une consommation de puissance faible sont obtenus en réalisant une conception conjointe front-end antenne. Avant de proposer l'architecture adaptée au cahier de charge, une étude préalable du canal de propagation à 60 GHz est faite. Les deux principales normes de canal IEEE, le 802.15.3c et le 802.11.ad, sont étudiées. L'analyse d'une architecture impulsionnelle mono-bande adaptée aux systèmes à faible consommation montre une limitation du débit quand des antennes non directives sont utilisées dans la norme de canal 802.11.ad. Afin de remédier à ce problème, une architecture multi-bande impulsionnelle MBOOK à récepteur non-cohérent est proposée. Cette architecture autorise un haut débit avec l'utilisation de quatre sous bandes. Elle conduit également à une consommation faible grâce à l'utilisation d'un récepteur non-cohérent et d'une topologie différentielle de l'émetteur évitant l'intégration de combineurs. Pour valider le concept d'architecture proposée, des antennes différentielles dédiées à l'architecture différentielle sont conçues. Les premières antennes sont de type patch différentiel excité par des lignes microrubans. Ces dernières présentent des caractéristiques de rayonnement adaptées aux besoins du cahier de charge. Néanmoins elles occupent une surface importante. Afin d'avoir une meilleure compacité, un patch alimenté par couplage à fente est développé. Il exploite deux polarisations linéaires orthogonales excitées par une paire d'entrées différentielles. Afin d'obtenir la directivité élevée nécessaire pour les scénarios LOS à 60 GHz sans utiliser de réseaux d'antennes ou de lentilles diélectriques, des métamatériaux sont utilisés. La mesure des antennes est basée sur la réalisation d'une transition guide d'onde WR-15 ligne microruban pour connecter l'antenne à l'analyseur de réseau. La mesure de l'antenne patch différentielle présente une bonne concordance avec les résultats de simulations. La technologie TQP15 de TriQuint est utilisée pour concevoir les différents éléments de la partie front-end. L'évaluation de la consommation globale d'émetteur valide l'architecture proposée en termes de faible consommation. Ce travail se termine par une évaluation du débit du système en tenant en compte de l'influence de l'antenne et du canal de propagation. Cette évaluation prouve la potentialité de l'architecture en termes de haut débit. On propose finalement une technique basée sur la technologie LTCC pour l'assemblage antenne/front-end / This work deals with the feasibility study of a radio architecture dedicated to mobile WPAN applications at 60 GHz and characterized by a low power consumption. Data rates of the order of Gbps, high compactness and low power consumption are obtained by co-designing the antenna and the front-end. Before proposing the architecture matching the specification needs, a preliminary study of the propagation channel at 60 GHz is made. The two main standards IEEE 802.15.3c and 802.11.ad the channel are studied. The analysis of a single-band architecture suitable for low-power systems shows a data rate limitation when directional antennas are used in the standard channel 802.11.ad. To address this problem, a multi-band impulse architecture MBOOK using a non-coherent receiver is proposed. This architecture allows high throughput with the use of four sub-bands. It also leads to a low power consumption through the use of a non-coherent receiver and a differential transmitter topology avoiding combiners. To validate the concept of the proposed architecture, differential antennas dedicated to the differential architecture are designed. Patch antennas excited by differential microstrip lines fulfil the needs of the specifications but occupy a large area. In order to miniaturize the antenna, slot-fed patch antennas are designed using two orthogonal linear polarizations excited by a pair of differential inputs. To achieve the high directivity required in LOS scenarios without using antenna arrays or dielectric lenses, metamaterials are used. The antenna measurement is based on the realization of a WR-15 waveguide-to-microstrip line transition to connect the antenna to the network analyzer. The differential measurement of the antenna patch exhibits a good agreement with the simulated results. The TriQuint's TQP15 technology is used to design the various circuits of the front-end. The emitter architecture is validated once the overall consumption has been evaluated. This work ends with an evaluation of the throughput of the system taking into account the influence of the antenna and the propagation channel. This evaluation shows the potential of the architecture in terms of high throughput. We finally propose an approach based on the LTCC technology for the antenna / front-end assembly

Wireless power transfer (WPT) technologies have become important for our everyday life. The most commonly used near-field WPT method is inductive coupling, which suffers from low efficiency and small range. The Strongly Coupled Magnetic Resonance (SCMR) method was developed recently, and it can be used to wirelessly transfer power with higher efficiency over a longer distance than the inductive coupling method. This dissertation develops new SCMR systems that have better performance compared to standard SCMR systems. Specifically, two new 3-D SCMR systems are designed to improve the angular misalignment sensitivity of WPT systems. Their power transfer efficiency for different angular misalignment positions are studied and analyzed. Prototypes are built for both systems and their performance is validated through measurement. Furthermore, new planar broadband conformal SCMR (CSCMR) systems are developed that maintain high efficiency while providing significantly larger bandwidth than standard CSCMR systems. Such broadband CSCMR systems are used here for the first time to simultaneously accomplish highly efficient wireless power transfer and high data rate communication through the same wireless link. These systems that combine wireless power and communication are expected to enable next-generation applications with battery-less and “power-hungry” sensors. Example applications include implantable and wearable sensors as well as embedded sensors for structural health monitoring.

Dispositivos integrados de sistemas-em-chip (SoC), especialmente aqueles dedicados às aplicações multimídia, processam grandes quantidades de dados armazenados em memórias. O desempenho das portas de memória afeta diretamente no desempenho do sistema. A melhor utilização do espaço de armazenamento de dados e a redução do custo e do consumo de potência dos sistemas eletrônicos encorajam o desenvolvimento de arquiteturas eficientes para controladores de memória. Essa melhoria deve ser alcançada tanto para interfaces com memórias internas quanto externas ao chip. Em sistemas de processamento de vídeo, por exemplo, memórias de grande capacidade são necessárias para armazenar vários quadros de imagem enquanto que os algoritmos de compressão fazem a busca por redundâncias. No caso de sistemas implementados em tecnologia FPGA é possível utilizar os blocos de memória disponíveis internamente ao FPGA, os quais são limitados a poucos mega-bytes de dados. Para aumentar a capacidade de armazenamento de dados é necessário usar elementos de memória externa e um núcleo de propriedade intelectual (IP) de controlador de memória é necessário. Contudo, seu desenvolvimento é uma tarefa muito complexa e nem sempre é possível utilizar uma solução "sob demanda". O uso de FPGAs para prototipar sistemas permite ao desenvolvedor integrar módulos rapidamente. Nesse caso, a verificação do projeto é uma questão importante a ser considerada no desenvolvimento de um sistema complexo. Controladores de memória de alta velocidade são extremamente sensíveis aos atrasos de propagação da lógica e do roteamento. A síntese a partir de uma descrição em linguagem de hardware (HDL) necessita da verificação de sua compatibilidade com as especificações de temporização pré-determinadas. Como solução para esse problema, é apresentado nesse trabalho um IP do controlador de memória DDR SDRAM com função de BIST (Built-In Self-Test) integrada, onde o teste de memória é utilizado para verificar o funcionamento correto do controlador. / Many integrated Systems-on-Chip (SoC) devices, specially those dedicated to multimedia applications, process large amounts of data stored on memories. The performance of the memories ports directly affects the performance of the system. Optimization of the usage of data storage and reduction of cost and power consumption of the electronic systems encourage the development of efficient architectures for memory controllers. This improvement must be reached either for embedded or external memories. In systems for video processing, for example, large memory arrays are needed to store several video frames while compression algorithms search for redundancies. In the case of FPGA system implementation, it is possible to use memory blocks available inside FPGA, but for only a few megabytes of data. To increase data storage capacity it is necessary to use external memory devices and a memory controller intellectual property (IP) core is required. Nevertheless, its development is a very complex task and it is not always possible to have a custom solution. Using FPGA for system prototyping allows the developer to perform rapid integration of modules to exercise a hardware version. In this case, test is an important issue to be considered in a complex system design. High speed memory controllers are very sensitive to gate and routing delays and the synthesis from a hardware description language (HDL) needs to be verified to comply with predefined timing specifications. To overcome these problems, a DDR SDRAM controller IP was developed which integrate the BIST (Built-In Self-Test) function, where the memory test is used to check the correct functioning of the DDR controller.

Dispositivos integrados de sistemas-em-chip (SoC), especialmente aqueles dedicados às aplicações multimídia, processam grandes quantidades de dados armazenados em memórias. O desempenho das portas de memória afeta diretamente no desempenho do sistema. A melhor utilização do espaço de armazenamento de dados e a redução do custo e do consumo de potência dos sistemas eletrônicos encorajam o desenvolvimento de arquiteturas eficientes para controladores de memória. Essa melhoria deve ser alcançada tanto para interfaces com memórias internas quanto externas ao chip. Em sistemas de processamento de vídeo, por exemplo, memórias de grande capacidade são necessárias para armazenar vários quadros de imagem enquanto que os algoritmos de compressão fazem a busca por redundâncias. No caso de sistemas implementados em tecnologia FPGA é possível utilizar os blocos de memória disponíveis internamente ao FPGA, os quais são limitados a poucos mega-bytes de dados. Para aumentar a capacidade de armazenamento de dados é necessário usar elementos de memória externa e um núcleo de propriedade intelectual (IP) de controlador de memória é necessário. Contudo, seu desenvolvimento é uma tarefa muito complexa e nem sempre é possível utilizar uma solução "sob demanda". O uso de FPGAs para prototipar sistemas permite ao desenvolvedor integrar módulos rapidamente. Nesse caso, a verificação do projeto é uma questão importante a ser considerada no desenvolvimento de um sistema complexo. Controladores de memória de alta velocidade são extremamente sensíveis aos atrasos de propagação da lógica e do roteamento. A síntese a partir de uma descrição em linguagem de hardware (HDL) necessita da verificação de sua compatibilidade com as especificações de temporização pré-determinadas. Como solução para esse problema, é apresentado nesse trabalho um IP do controlador de memória DDR SDRAM com função de BIST (Built-In Self-Test) integrada, onde o teste de memória é utilizado para verificar o funcionamento correto do controlador. / Many integrated Systems-on-Chip (SoC) devices, specially those dedicated to multimedia applications, process large amounts of data stored on memories. The performance of the memories ports directly affects the performance of the system. Optimization of the usage of data storage and reduction of cost and power consumption of the electronic systems encourage the development of efficient architectures for memory controllers. This improvement must be reached either for embedded or external memories. In systems for video processing, for example, large memory arrays are needed to store several video frames while compression algorithms search for redundancies. In the case of FPGA system implementation, it is possible to use memory blocks available inside FPGA, but for only a few megabytes of data. To increase data storage capacity it is necessary to use external memory devices and a memory controller intellectual property (IP) core is required. Nevertheless, its development is a very complex task and it is not always possible to have a custom solution. Using FPGA for system prototyping allows the developer to perform rapid integration of modules to exercise a hardware version. In this case, test is an important issue to be considered in a complex system design. High speed memory controllers are very sensitive to gate and routing delays and the synthesis from a hardware description language (HDL) needs to be verified to comply with predefined timing specifications. To overcome these problems, a DDR SDRAM controller IP was developed which integrate the BIST (Built-In Self-Test) function, where the memory test is used to check the correct functioning of the DDR controller.

Dispositivos integrados de sistemas-em-chip (SoC), especialmente aqueles dedicados às aplicações multimídia, processam grandes quantidades de dados armazenados em memórias. O desempenho das portas de memória afeta diretamente no desempenho do sistema. A melhor utilização do espaço de armazenamento de dados e a redução do custo e do consumo de potência dos sistemas eletrônicos encorajam o desenvolvimento de arquiteturas eficientes para controladores de memória. Essa melhoria deve ser alcançada tanto para interfaces com memórias internas quanto externas ao chip. Em sistemas de processamento de vídeo, por exemplo, memórias de grande capacidade são necessárias para armazenar vários quadros de imagem enquanto que os algoritmos de compressão fazem a busca por redundâncias. No caso de sistemas implementados em tecnologia FPGA é possível utilizar os blocos de memória disponíveis internamente ao FPGA, os quais são limitados a poucos mega-bytes de dados. Para aumentar a capacidade de armazenamento de dados é necessário usar elementos de memória externa e um núcleo de propriedade intelectual (IP) de controlador de memória é necessário. Contudo, seu desenvolvimento é uma tarefa muito complexa e nem sempre é possível utilizar uma solução "sob demanda". O uso de FPGAs para prototipar sistemas permite ao desenvolvedor integrar módulos rapidamente. Nesse caso, a verificação do projeto é uma questão importante a ser considerada no desenvolvimento de um sistema complexo. Controladores de memória de alta velocidade são extremamente sensíveis aos atrasos de propagação da lógica e do roteamento. A síntese a partir de uma descrição em linguagem de hardware (HDL) necessita da verificação de sua compatibilidade com as especificações de temporização pré-determinadas. Como solução para esse problema, é apresentado nesse trabalho um IP do controlador de memória DDR SDRAM com função de BIST (Built-In Self-Test) integrada, onde o teste de memória é utilizado para verificar o funcionamento correto do controlador. / Many integrated Systems-on-Chip (SoC) devices, specially those dedicated to multimedia applications, process large amounts of data stored on memories. The performance of the memories ports directly affects the performance of the system. Optimization of the usage of data storage and reduction of cost and power consumption of the electronic systems encourage the development of efficient architectures for memory controllers. This improvement must be reached either for embedded or external memories. In systems for video processing, for example, large memory arrays are needed to store several video frames while compression algorithms search for redundancies. In the case of FPGA system implementation, it is possible to use memory blocks available inside FPGA, but for only a few megabytes of data. To increase data storage capacity it is necessary to use external memory devices and a memory controller intellectual property (IP) core is required. Nevertheless, its development is a very complex task and it is not always possible to have a custom solution. Using FPGA for system prototyping allows the developer to perform rapid integration of modules to exercise a hardware version. In this case, test is an important issue to be considered in a complex system design. High speed memory controllers are very sensitive to gate and routing delays and the synthesis from a hardware description language (HDL) needs to be verified to comply with predefined timing specifications. To overcome these problems, a DDR SDRAM controller IP was developed which integrate the BIST (Built-In Self-Test) function, where the memory test is used to check the correct functioning of the DDR controller.

HF communication has been used for more than a century and to this day still fulfils an important function in communications networks. In order to interface with modern communications protocols, solutions have to be designed to facilitate data communication over HF (High Frequency). STANAG 5066 is one such solution which provides an application independent ARQ (Automatic Repeat Request) bearer service for client applications. A need exists within the STANAG 5066 specification for a DRC algorithm. The objective of such an algorithm is to select the optimum data rate and interleaver size, based upon current HF channel conditions, to maximise the data throughput over the HF link. In this dissertation previous implementations of DRC algorithms were studied and evaluated. In literature it was found that algorithm implementations used the FER and no channel information to make a data rate choice. This resulted in algorithms that tended to oscillate between data rate choices, and was very slow to react to changes in the HF channel. A new DRC algorithm was designed and simulated that uses the SNR (Signal-to-Noise Ratio) and the BER estimate to make a data rate choice. The DRC algorithm was implemented in a commercial STANAG 5066 system and tested using HF data modems and a simulated HF channel. The results of the implementation and testing show that the designed DRC algorithm gives a better performance, is quicker to adapt and is more robust than previous DRC algorithms. This is also the first DRC algorithm that has been designed to use channel information, such as the SNR and BER, to make a data rate choice. / Dissertation (MEng)--University of Pretoria, 2007. / Electrical, Electronic and Computer Engineering / unrestricted

Un des objectifs majeurs des systèmes de communication est de pouvoir transmettre des données aux plus hauts débits possibles. La demande croissante des utilisateurs pour la communication sans fil à haut débit excède déjà les possibilités des réseaux actuels. Afin de répondre à cette problématique, nous présentons des systèmes de communication basés sur des fréquences porteuses térahertz (THz), fréquences suffisamment élevées pour supporter des débits supérieurs à la centaine de gigahertz. En particulier, nous nous intéressons au développement et à l'intégration d'un détecteur haut débit destiné à la communication THz sans fil. Nous utilisons comme détecteur un transistor GaAs à haute mobilité électronique (HEMT). Contrairement aux détecteurs existants tels que les diodes Schottky, le transistor étudié offre des avantages en ce qui concerne le coût, la compacité et les performances. En particulier, l'impédance de sortie est mieux adaptée aux circuits intégrés hauts débits d'impédance d'entrée de 50 Ohm. Nous présentons une caractérisation de ce détecteur en sensibilité et en bande passante de modulation, démontrant pour la première fois sa capacité à être utilisé pour des communications à haut débit. L'intégration du transistor, indispensable à la réalisation de communications réelles, est détaillée. Une communication THz sans fil est démontrée à des fréquences de 0,200 THz et 0,309 THz. Pour la première fois, une transmission de données sans erreur a été démontrée jusqu'à un débit de 8,2 Gbps avec un transistor GaAs HEMT à une fréquence porteuse de 0,309 THz. Enfin, nous présentons de nouveaux transistors avec antenne intégrée permettant des communications à plus haut débit et de plus grande portée, grâce à une meilleure sensibilité. / One of the major objectives of communication systems is the ability to transmit data at the highest possible rates. The ever-growing user demand for wireless communication already exceeds capacities of present networks.In order to solve this problem, we introduce communication systems based on terahertz (THz) high-frequency carriers, whose frequencies are high enough to support data-rates higher than a hundred of gigahertz. In particular, we are interested in the development and the integration of a high data-rate detector intended for THz wireless communication.We use a GaAs High-electron-mobility transistor (HEMT) as detector. Unlike existing detectors such as Schottky diodes, the transistor studied in this thesis offers advantages in terms of cost, compactness and performances. In particular, the output impedance is more suitable for high data-rate integrated circuits whose input impedance is 50 Ohm. We present the characterization of the detector in terms of sensitivity and modulation bandwidth, demonstrating for the first time its ability to be used for high data-rate communications. The transistor's integration, essential for real communications, is detailed.A wireless THz communication is demonstrated around 0.200 THz and 0.309 THz. For the first time, an error-free transmission at data-rates up to 8.2 Gbps is demonstrated, using a GaAs plasma wave HEMT and a 0.309 THz carrier frequency. Finally, we present new transistors with integrated antenna, allowing communications at higher data-rates and with a longer range, thanks to a better sensitivity.