Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro / m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta / -&Sigma / DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.

The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.

Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά ενός νέου μετατροπέα ψηφιακού σήματος σε αναλογικό (Digital to Analog Converter DAC). Η δομή του DAC βασίζεται στη γνωστή δομή του συμβατικού R2R Ladder και θα μπορούσε να θεωρηθεί σαν μία δισδιάστατη ανάπτυξη του Ladder. Αυτό σημαίνει ότι η νέα μορφή του DAC χρησιμοποιεί σαφώς περισσότερες αντιστάσεις από τον συμβατικό Ladder, όμως δίνεται η δυνατότητα της ρύθμισης του ρεύματος εξόδου του κάθε κλάδου. Αυτό έχει ως συνέπεια τη δραματική βελτίωση της γραμμικότητας του DAC. Επιπλέον στην Εργασία αυτή μελετήθηκαν με χρήση της θεωρίας των πιθανοτήτων τα χαρακτηριστικά του απλού Ladder και χρησιμοποιήθηκαν για την εξαγωγή συμπερασμάτων που αφορούν στη γραμμικότητα της νέας δομής Ladder. Τα θεωρητικά αποτελέσματα επιβεβαιώθηκαν με εξομοιώσεις. Τέλος, μία σχεδίαση σε φυσικό επίπεδο με την χρήση μόνο MOSFETS και CMOS τεχνολογίας (χωρίς την χρήση αντιστάσεων) σχεδιάσθηκε και εξομοιώθηκε στο Cadence ένας Ladder της νέας δομής. / This Diploma Thesis studies on a new Digital to Analog Converter (DAC) structure developed in the Applied Electronics Laboratory of the University of Patras. The new DAC structure is based on the simple R2R ladder combining several of them in a 2-dimentional grid. As result a high linearity DAC is derived after a simple calibration procedure. The Diploma Thesis presents results on probability of the simple R2R Ladder, employs these results so as to forecast the linearity of the 2-dimentional Ladder, whereas confirms theoretical results with simulations. Finally, a DAC based on the 2-dimentional topology has been designed and simulated using Cadence, in the framework of this Diploma Thesis.

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

L'utilisation des ondes électromagnétiques, en tant que moyen de transmission d'informations entre les terminaux mobiles, a rapidement conduit à une congestion du spectre fréquentiel. Pour améliorer le flux de données entre utilisateurs, les autorités réglementent l'accès aux bandes de fréquences en imposant des normes strictes aux télécommunications mobiles. Ainsi, et afin d'accroître leurs capacités d'échange de données, les prochaines générations de terminaux mobiles doivent utiliser dynamiquement les ressources spectrales. Ces contraintes affectent la conception des émetteurs-récepteurs mobiles. Ils doivent transmettre des débits de données élevés en utilisant plusieurs porteuses ayant différentes modulations, tout en consommant le moins d'énergie possible, afin d'économiser l’autonomie de leurs batteries. L'émetteur Walsh tente de répondre à ces défis / The use of electromagnetic waves, as a medium for transmitting information between the mobile terminals, has quickly lead to a congestion of the frequency spectrum. To improve the data traffic flow between users, the authorities regulate the access to the frequency bands by imposing stringent standards to the mobile telecommunication. Thus, and in order to increase their data exchange capabilities, the next generations of mobile terminals have to dynamically use the spectral resources. These constraints affect the design of mobile transceivers. They must transmit high data rates by using multiple carriers and various modulation schemes, while consuming as less energy as possible, in order to save their battery life. The Walsh transmitter tries to answer these challenges.

Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform, usually a sine wave, by generating a time varying signal in digital form a then performing a digital to analog conversion. Because operations within a DDFS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution and operation over a broad spectrum of frequencies.

The subject of this thesis is design and construction of a periodic signal generator prototype. The generator will use Atmel XMEGA128A4U microcontroller with computer control managed via USB interface. The thesis contains general solutions to the problem of generating signals with a special focus on utilization of DA converter – digital synthesis and reconstruction of the signal from DA converter output to continuous signal. The thesis further deals with implementation of the USB layer using two libraries (LUFA library on microcontroller side and LubUsbDotNet library on computer side). The final solution will include DC step-up converter for signal peak amplitude assessment and summing amplifier for adding the DC voltage to the output signal. The application will allow for generating signals of various shapes including user-defined ones. These signals will be displayed in the actual application window. There, users will be allowed to create user-defined signal in easy-to-use GUI or load it directly from a file.

Wireless communication technologies continue to evolve to meet the demand for increased data throughput. To achieve higher data throughput one approach is to increase the bandwidth. One problem related to very large bandwidths is the implementation of digital-to-analog converters with sampling rates roughly in the 5 to 20 GHz range. Traditionally, current-steering data converters have been the go-to choice but their linearity suffers at higher frequencies. An alternative to the current-steering digital-to-analog converter is the voltage-mode digital-to-analog converter, which is an attractive option for integration into digital intensive application-specific integrated circuits due to its digital-in-nature architecture. In this thesis, a resistive voltage-mode digital-to-analog converter with an integrated low-dropout voltage regulator is proposed for a sampling rate of 16 GSps. The proposed resistive voltage-mode digital-to-analog converter with an output impedance matched to a 100 Ω load, achieves a spurious-free dynamic range of 64 dBc and intermodulation distortion of 66 dBc for output frequencies up to 5.5 GHz in the worst process corner.

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