Finally, another new 0.5V fully differential wideband amplifier, which can be used in the wideband modulator, has been proposed. The gate-input two-stage amplifier employs a DC common-mode feedback circuit that uses a Miller-amplified capacitor for its frequency compensation. With the proposed technique, the power consumption of the low-voltage amplifier is drastically reduced. / Furthermore, a new dynamic CM level shifting technique for low-voltage CT delta-sigma modulators that employ a return-to-open feedback DAC is reported in the thesis. The technique maintains a stable CM level at the amplifier's inputs for this type of modulators. Simulation results show that it improves the modulator's SNDR by 11%. / In this thesis, we present research works on developing a low-voltage delta-sigma modulator with a wide signal bandwidth. Specifically, a 0.5V complex low-pass continuous-time (CT) third-order delta-sigma modulator that has a single-sided signal bandwidth of 1MHz, targeting for application in Bluetooth receivers, is presented without using any internal voltage boosting techniques which are potentially harmful to the reliability of the device. The wide bandwidth of the modulator at this low supply voltage is enabled by a special common-mode (CM) level arrangement in the system level and by new low-voltage amplifies. Realized in a 0.13mum CMOS process the proposed modulator achieves a 61.9-dB peak signal-to-noise-and-distortion ratio at the nominal supply of 0.5V with 3.4mW consumption, and occupies an active area of 0.9mm2. The modulator achieves the best figure-of-merit among its class. / The development of low-voltage design techniques for analog circuits has recently received a lot of attention due to the continuous shrinking of the supply voltage in modern CMOS technologies, which is projected to reduce to 0.5V for low power applications within ten years in the International Technology Roadmap for Semiconductor. This thesis focuses on developing circuit techniques for low-voltage delta-sigma modulator, a functional block that is widely used in mixed-signal integrated circuits. Several delta-sigma modulators operating at supply voltages below 0.9V have been reported in the open literature. However, none of them supports a signal bandwidth wider than 100kHz with a reasonable performance. / He, Xiaoyong. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 104-111). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

Thesis (Ph. D.)--Carleton University, 2001. / Includes bibliographical references (p. 296-303). Also available in electronic format on the Internet.

Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά, ενός καινοτόμου Μετατροπέα Ψηφιακού Σήματος σε Αναλογικό (Digital to Analog Converter - DAC) που αναπτύχθηκε στο Εργαστήριο Ηλεκτρονικών Εφαρμογών του Πανεπιστημίου Πατρών. Η δομή του συγκεκριμένου DAC βασίζεται στην τοπολογία του γνωστού R-2R Ladder και παρ’ όλο που υλοποιείται με αντιστάσεις μικρής σχετικά ακρίβειας, επιτυγχάνει τελικά πολύ υψηλές επιδόσεις σε γραμμικότητα, κατανάλωση αλλά και επιφάνεια υλοποίησης. Στα πλαίσια της παρούσας Διπλωματικής Εργασίας χρησιμοποιήθηκε το ‘κατά κοινή ομολογία’ καλύτερο λογισμικό σχεδίασης και εξομοίωσης ολοκληρωμένων ηλεκτρονικών κυκλωμάτων, το Cadence. Με τη βοήθεια αυτού του Cadence εξομοιώσαμε την νέα τοπολογία DAC και ελέγξαμε την δυνατότητα προσέγγισης της υψηλής γραμμικότητας που παρουσιάζεται στις ερευνητικές εργασίες που βασιστήκαμε. Επιπλέον, έγινε και μία υλοποίηση σε φυσικό επίπεδο με τη χρήση του λογισμικού Cadence, δηλαδή σχεδιάστηκε η τοπολογία του κυκλώματος στο πυρίτιο για τη δημιουργία ολοκληρωμένου συστήματος (system on chip). / This Diploma Thesis studies on an innovative Digital to Analog Converter (DAC) structure developed in the Applied Electronics Laboratory of the Electrical and Computer Engineering Department, University of Patras. This new DAC structure is based on the well-known R-2R Ladder, and is capable to achieve very high linearity on high resolution DAC without requiring resistances of high accuracy, while preserving at the same time the good characteristics of the conventional R-2R ladder in terms of speed, power consumption and implementation area. The state of the art EDA tool, Cadence was employed in the framework of this Diploma Thesis in order to simulate the behavior of the DAC and to certify its enhanced characteristics regarding the linearity. Additionally, the same EDA tool was employed for designing the DAC topology on a silicon chip.

Ko, Chi Tung. / On t.p. "delta" and "sigma" appear as the Greek letters. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.1 / 摘要 --- p.3 / Acknowledgements --- p.4 / Table of Contents --- p.5 / List of Figures --- p.8 / List of Tables --- p.13 / Chapter Chapter 1 --- Introduction --- p.14 / Chapter 1.1 --- Motivation --- p.14 / Chapter 1.2 --- Objectives --- p.17 / Chapter 1.3 --- Organization of the Thesis --- p.17 / References --- p.18 / Chapter Chapter 2 --- Fundamentals of Delta-sigma Modulators --- p.20 / Chapter 2.1 --- Delta-sigma Modulator as a Feedback System --- p.20 / Chapter 2.2 --- Quantization Noise --- p.22 / Chapter 2.3 --- Oversampling --- p.23 / Chapter 2.4 --- Noise Shaping --- p.25 / Chapter 2.5 --- Performance Parameters --- p.27 / Chapter 2.6 --- Baseband Modulators vs Bandpass Modulators --- p.27 / Chapter 2.7 --- Discrete-time Modulators vs Continuous-time Modulators --- p.28 / Chapter 2.8 --- Single-bit Modulators vs Multi-bit Modulators --- p.29 / Chapter 2.9 --- Non-linearity and Image Problems in Multi-bit Delta-sigma Modulators --- p.29 / Chapter 2.9.1 --- Non-linearity Problem --- p.29 / Chapter 2.9.2 --- Image Problem --- p.31 / Reference --- p.36 / Chapter Chapter 3 --- Image Rejection and Non-linearity Suppression Techniques for Quadrature Multi-bit Δ¡♭ Modulators --- p.38 / Chapter 3.1 --- Quadrature DEM Technique --- p.38 / Chapter 3.1.1 --- Introduction and Working Principle --- p.38 / Chapter 3.1.2 --- Behavioral Simulation Results --- p.42 / Chapter 3.2 --- IQ DWA Technique --- p.44 / Chapter 3.2.1 --- Introduction and Working Principle --- p.44 / Chapter 3.2.2 --- Behavioral Simulation Results --- p.49 / Chapter 3.3 --- DWA and Bit-wise Data-Dependent DEM --- p.52 / Chapter 3.3.1 --- Introduction and Working Principle --- p.52 / Chapter 3.3.2 --- Behavioral Simulation Results --- p.54 / Chapter 3.4 --- Image Rejection Technique for Quadrature Mixer --- p.61 / Chapter 3.5 --- Conclusion --- p.63 / Reference --- p.64 / Chapter Chapter 4 --- System Design of a Multi-Bit CT Modulator for GSM/WCDMA Application --- p.65 / Chapter 4.1 --- Objective of Design and Design Specification --- p.65 / Chapter 4.2 --- Topology Selection --- p.65 / Chapter 4.3 --- Discrete-time Noise Transfer Function Generation --- p.66 / Chapter 4.4 --- Continuous-time Loop Filter Transfer Function Generation --- p.69 / Chapter 4.5 --- Behavioral Model of Modulator --- p.69 / Chapter 4.6 --- Dynamic Range Scaling --- p.75 / Chapter 4.7 --- Behavioral Modeling of Operational Amplifiers --- p.77 / Chapter 4.8 --- Impact of RC Variation on Performance --- p.85 / Chapter 4.9 --- Loop Filter Component Values --- p.88 / Chapter 4.10 --- Summary --- p.90 / Reference --- p.90 / Chapter Chapter 5 --- Transistor-level Implementation of Modulators --- p.92 / Chapter 5.1 --- Overview of Design --- p.92 / Chapter 5.2 --- Design of Operational Transconductance Amplifiers (OTAs) --- p.94 / Chapter 5.2.1 --- First Stage --- p.94 / Chapter 5.2.2 --- Second and Third Stages --- p.98 / Chapter 5.3 --- Design of Feed-forward Transconductance (Gm) Cells --- p.101 / Chapter 5.4 --- Design of Quantizer --- p.102 / Chapter 5.4.1 --- Reference Ladder Design --- p.102 / Chapter 5.4.2 --- Comparator Design --- p.104 / Chapter 5.5 --- Design of Feedback Digital-to-Analog Converter (DAC) --- p.106 / Chapter 5.5.1 --- DWA and DEM Logic --- p.107 / Chapter 5.5.2 --- DAC Circuit --- p.109 / Chapter 5.6 --- Design of Integrated Mixers --- p.111 / Chapter 5.7 --- Design of Clock Generators --- p.112 / Chapter 5.7.1 --- Master Clock Generator --- p.112 / Chapter 5.7.2 --- LO Clock Generator --- p.114 / Chapter 5.7.3 --- Simulation Results --- p.116 / Reference --- p.125 / Chapter Chapter 6 --- Physical Design of Modulators --- p.127 / Chapter 6.1 --- Floor Planning of Modulator --- p.127 / Chapter 6.2 --- Shielding of Sensitive Signals --- p.130 / Chapter 6.3 --- Common Centroid Layout --- p.130 / Chapter 6.4 --- Amplifier Layout --- p.132 / Reference --- p.137 / Chapter Chapter 7 --- Conclusions --- p.138 / Chapter 7.1 --- Conclusions --- p.138 / Chapter 7.2 --- Future Works --- p.138 / Appendix A Schematics of Building Blocks --- p.140 / First Stage Operational Amplifier --- p.140 / First Stage Amplifier Local Bias Circuit --- p.140 / Second and Third Stage Operational Amplifier --- p.141 / Second and Third Stage Local Bias Circuit --- p.141 / CMFB Circuit (First Stage) --- p.142 / CMFB Circuit (Second Stage) --- p.142 / Gm-Feed-forward Cells --- p.143 / Gm Feed-forward Cell Bias Circuit --- p.143 / Reference Ladder Circuit --- p.144 / Pre-amplifier Circuit --- p.145 / Latch Circuit --- p.145 / DAC Circuit (Unit Cell) --- p.146 / Author's Publications --- p.147

In an increasingly digital world, the need for high speed and high fidelity analog-to-digital (A/D) converters is paramount. Performance improvements in electronic A/Ds have not kept pace with demand, hence the need to consider alternative technologies. One such technology is photonics, as it takes advantage of optical sampling, high speed optical switches and low cross-talk interconnects. Optical sampling derives its advantage from the application of ultra low timing jitter (<100fs) mode locked lasers utilised to provide high speed clock pulses. In this thesis the feasibility and simulated performance of three different types of photonic oversampled A/D converters was investigated. The first, and simplest design is that of oversampled pulse-code-modulation (PCM), where a 2-level photonic comparator is used to sample the analog input at a frequency much greater than the Nyquist frequency. Subsequent low pass filtering produces a digital representation of the input. The other two architectures that were investigated are the first-order sigma-delta and error diffusion, which add one level of error correction to the PCM technique. These two architectures require the functional elements of a subtractor, comparator and delay. The photonic comparator and subtractor functionality was provided by Self-Electro-Optic Effect devices (SEED) based upon multiple quantum well (MQW) p-i-n devices. To facilitate calculation of the performance of the different architectures and aid in device design, a simulation of SEED operation based upon experimental data was developed. The simulation’s accuracy was demonstrated by agreement with the results from experimental S-SEED switching and optical subtraction. To emphasize the utility of the model, the simulation was subsequently used to demonstrate tristability of an S-SEED and critical slowing down in a bistable S-SEED. These effects were experimentally verified. To provide enhanced comparator contrast ratio and subtractor dynamic range, resonantly enhanced microcavity multiple quantum well (MQW) p-i-n devices were designed and grown by MOCVD. The operation of the subtractor and comparator was experimentally demonstrated and utilising temperature tuning, optimised performance was achieved with devices from the same wafer. Furthermore, the inclusion of gain was shown to improve the subtractor performance to that demanded by the sigma-delta. The constraints on each architecture imposed by the unipolar nature of the light intensity were derived and the sigma delta architecture was shown to be superior to the error diffusion for a photonic implementation. Using the numerical simulation based upon experimentally derived data, the entire sigma delta architecture was simulated to calculate the expected performance. The signal-to-quantisation-noise ratio (SQNR) was calculated as a function input amplitude and a peak SQNR of 54dB was obtained for an oversampling ratio of 100. / http://library.adelaide.edu.au/cgi-bin/Pwebrecon.cgi?BBID=1283979 / Thesis (Ph.D.) -- University of Adelaide, School of Chemistry and Physics, 2007

Graduation date: 2006 / The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

In a number of electrical engineering problems, so-called "crossing points" -- the instants at which two continuous-time signals cross each other -- are of interest. Often, particularly in applications using a Digital Signal Processor (DSP), only periodic samples along with a partial statistical characterization of the signals are available. In this situation, we are faced with the following problem: Given limited information about these signals, how can we efficiently and accurately estimate their crossing points? / For example, an audio amplifier typically receives its input from a digital source decoded into regular samples (e.g. from MP3, DVD, or CD audio), or obtained from a continuous-time signal using an analog-to-digital converter (ADC). In a switching amplifier based on Pulse-Width Modulation (PWM) or Click Modulation (CM), a signal derived from the sampled audio is compared against a deterministic reference waveform; the crossing points of these signals control a switching power stage. Crossing-point estimates must be accurate in order to preserve audio quality. They must also be simple to calculate, in order to minimize processing requirements and delays. / We consider estimating the crossing points of a known function and a Gaussian random process, given uniformly-spaced, noisy samples of the random process for which the second-order statistics are assumed to be known. We derive the Maximum A-Posteriori (MAP) estimator, along with a Minimum Mean-Squared Error (MMSE) estimator which we show to be a computationally efficient approximation to the MAP estimator. / We also derive the Cramer-Rao bound (CRB) on estimator variance for the problem, which allows practical estimators to be evaluated against a best-case performance limit. We investigate several comparison estimators chosen from the literature. The structure of the MMSE estimator and comparison estimators is shown to be very similar, making the difference in computational expense between each technique largely dependent on the cost of evaluating various (generally non-linear) functions. / Simulations for both Pulse-Width and Click Modulation scenarios show the MMSE estimator performs very near to the Cramer-Rao bound and outperforms the alternative estimators selected from the literature.