Este trabalho apresenta uma arquitetura de hardware para a predição intra-quadro do padrão emergente HEVC de codificação de vídeo. O padrão HEVC está sendo desenvolvido tendo como principal objetivo o aumento em 50% na eficiência de compressão, quando comparado com o padrão H.264/AVC, atual padrão estado da arte na codificação de vídeos. Para atingir este objetivo, várias novas ferramentas de codificação foram desenvolvidas para serem introduzidas no novo padrão HEVC. Embora essas novas ferramentas tenham obtido êxito em aumentar a eficiência de compressão do novo padrão HEVC, elas também colaboraram para o aumento da complexidade computacional no processo de codificação. Analisando somente os avanços na predição intra-quadro, em comparação com o padrão H.264/AVC, é possível perceber que vários novos modos direcionais de codificação foram inseridos no processo de predição. Além disso, existem mais tamanhos de blocos que podem ser considerados pela predição intra-quadro. Nesse contexto, este trabalho propõe o uso de duas abordagens para melhorar o desempenho da predição intra-quadro em codificadores HEVC. Primeiramente, foram desenvolvidos algoritmos rápidos de decisão de modo, baseados em heurísticas, para a predição intra-quadro. Os resultados mostraram que é possível reduzir a complexidade computacional do processo de predição intra-quadro com pequenas perdas na eficiência de compressão (taxa de bits e qualidade visual). No pior caso, a perda foi de 6.9% na taxa de bits e de 0.12dB na qualidade, para uma redução de 35% no tempo de processamento. Em seguida, utilizando um dos algoritmos desenvolvidos, uma arquitetura de hardware para a predição intra-quadro foi desenvolvida. Além da redução de complexidade proporcionada pelo uso do algoritmo desenvolvido, técnicas de desenvolvido de hardware, tais como aumento no nível de paralelismo e uso de pipeline, também foram utilizadas para melhorar o desempenho da arquitetura desenvolvida. Os resultados de síntese da arquitetura para a tecnologia IBM 0,65um mostram que ela é capaz de operar a 500MHz, atingindo uma taxa de processamento suficiente para realizar a predição intra-quadro de mais de 30 quadros por segundo para resoluções como Full HD (1920x1080pixels). / This work presents an intra-frame prediction hardware architecture targeting the emerging HEVC video coding standard. The HEVC standard is being developed with the main goal of increase the compression efficiency in 50% when compared to the latest H.264/AVC video coding standard. To achieve such a goal, several new video coding strategies were developed to be used in the HEVC. Although these strategies have increased the compression efficiency of the emerging HEVC standard, it also increased the computational complexity of the encoding process. Looking only to the intra prediction process, several new directional modes are used to perform the prediction. Besides, there are more block sizes that can be supported by the intra prediction process. This work proposes to use two different approaches to improve the HEVC intra prediction performance. First we developed fast intra mode decision algorithms, showing that it is possible to decrease the intra prediction computational complexity with negligible loss in the compression performance (bit-rate and video quality). In the worst case, the bit-rate loss was 6.99% and the PSNR loss was 0.12dB in average allowing reducing the encoding time up to 35%. Then, using the developed fast algorithms as base, this work proposes an intra prediction hardware architecture. The designed architecture was specifically based on one of the developed fast intra mode decision algorithms. Besides, hardware techniques such as increase the parallelism level and pipeline were also used to improve the intra prediction performance. The synthesis results for the IBM 0.65nm have shown that the architecture is able to achieve 500MHz as maximum operation frequency. This way, the architecture throughput is enough to perform the intra prediction process for more than 30 frames per second considering high resolution digital videos, such as Full HD (1920x1080).

A compressão de vídeo é essencial para aplicações de vídeo digital. Devido ao elevado volume de informações contidas em um vídeo digital, um processo de compressão é aplicado antes de ser armazenado ou transmitido. O padrão H.264/AVC é considerado o estado-da-arte em termos de compressão de vídeo, introduzindo um conjunto de ferramentas inovadoras em relação a padrões anteriores. Tais ferramentas possibilitam um ganho significativo em compressão, ao preço de um aumento na complexidade. A predição intra-quadro é uma das ferramentas inovadoras do padrão H.264/AVC, responsável por reduzir a redundância espacial do vídeo utilizando informações contidas em um único quadro para predição. A predição intra-quadro do H.264/AVC possibilita ganhos de compressão em comparação com os mais usados padrões de compressão de imagens estáticas, o JPEG e JPEG 2000, mas introduz complexidade no projeto do codificador de vídeo, especialmente quando se torna necessário atingir o desempenho para codificar vídeos de alta definição em tempo-real. Neste contexto, a presente dissertação apresenta a proposta e o desenvolvimento de uma arquitetura de hardware dedicada para a predição intra-quadro, presente nos codificadores compatíveis com o padrão H.264/AVC de compressão de vídeo. A arquitetura desenvolvida codifica vídeos de alta definição em tempo-real utilizando uma frequência de operação 46% menor que o melhor trabalho encontrado na literatura. A arquitetura desenvolvida será integrada, futuramente, em um codificador de vídeo em hardware compatível com o padrão H.264/AVC no perfil Main. / Video coding is essential in digital video applications, due to the extremely high data volume present in a digital video to be stored or transmitted through a physical link. H.264/AVC is the state-of-the-art video coding standard, introducing a set of novel features when compared to former standards. A significant gain in terms of bit-rate has been obtained but the increase of complexity of the codec when compared to other video coding standard is inevitable. Intra-frame Prediction is a novel feature introduced with H.264/AVC, which is responsible for reducing a video spatial redundancy using only information in the same frame for prediction. H.264/AVC intra-frame prediction can provide compression gains when compared with state-of-art still image coding standards, like JPEG and JPEG 2000, but introduces complexity and latency to video encoder design, mainly when high definition video coding is needed. In this context, this thesis presents the proposal and development of an intra-frame prediction dedicated hardware architecture for H.264/AVC compatible video encoder. The developed architecture achieved the performance to encode high definition video in real-time with 46% reduction in clock frequency compared with the best results found in the literature. In the future, the developed architecture can be integrated to a fully compatible H.264/AVC main profile hardware encoder.

Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.:1 Introduction 1.1 Forethoughts 1.2 Theoretical Background 1.2.1 Definitions 1.2.2 Expressing Connections between Circuit Elements 1.2.3 Global Context and Target Function 1.2.4 Problem formulation as QBF and SAT 2 Description of the Implemented Tool 2.1 Design Decisions 2.1.1 Choice of Language, Libraries and Frameworks 2.1.2 Solving the QBF Problem 2.1.3 Design of the Internally Used Meta-Model 2.1.4 User Interface Ergonomics 2.1.5 Aspects of Schematic Visualization 2.1.6 Limitations 2.2 Implemented Features 2.2.1 Basic Interaction 2.2.2 User-Defined Components 2.2.3 Generation of Circuit Symbols 2.2.4 Methods for Specifying Functional Behaviour 3 Implementation Details 3.1 Classes Involved in the Component Meta-Model 3.2 The Document Entry Class and its Factory 3.3 Model and View 3.3.1 The Model Element Hierarchy 3.3.2 The Schematics Element Hierarchy 3.4 The Quantor Interface 4 An Example Workflow 4.1 The Task 4.2 A Component Descriptor for Xilinx’ LUT6-2 4.3 Designing the Model 4.4 Computing the Desired Configuration 5 Summary and Outlook 5.1 Achieved Results 5.2 Suggested Improvements References A Acronyms and Glossary B UML Diagrams

A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the three unsolved engineering problems in SiLago design. First, power characterization of the flat design which was designed using the SiLago methodology. Second, designing a hierarchical clock tree and harden it inside the SiLago logic. Third, dimensioning hierarchical power grids. Out of these, clock tree illustrates some interesting characteristics as it is programmable and predictable.The tools used for digital designing are Cadence Innovus, Synopsys Design Vision, and Mentor Graphics Questasim. These are very sophisticated tools and widely accepted in industries as well as in academia.The work done in this thesis has enabled SiLago platform one step forward toward its fruition. / En hårdvarudesign metodologi eller plattform är komplett om den har kapabiliteten till att lyckas genomföra klockträdet, förutsäga strömförbrukningen för bästa och värsta fall av Parasitic Interconnect Corners (RC Corners), tillföra kraft till varje standardcell, etc. Denna avhandling har försökt lösa de tre olösta tekniska problemen i SiLago-designen. Det första är strömkvalificering av designen som designades med hjälp av SiLago metoden. Det andra problemet är att designa ett hierarkiskt klockträd och härda det inuti SiLago logik. Det tredje problemet är att dimensionera hierarkiska strömnät. Ur dessa illustrerar klockträdet några intressanta egenskaper eftersom det är programmerbart och förutsägbart. De verktyg som används för digital design är Cadence Innovus, Synopsys Design Visionoch Mentor Graphics Questasim. Dessa verktyg är mycket sofistikerade och allmänt accepterade i industrier såväl som i akademin. Arbetet i denna avhandling har gjort det möjligt för SiLago-plattformen att ta ett steg mot att realiseras.

<p>  </p> <p>Knot tying boards are low fidelity surgical simulators used to practice tying suture, but devices on the market currently provide no feedback and no way of changing out bands. A simple-to-use knot tying board with interchangeable bands capable of measuring force was designed. This board is comparable in cost to products currently available on the market. The knot tying board was then prototyped and tested. Four MD students completed trials of one-handed and two-handed knot tying with three throws per trail. In testing, the knot tying board was capable of measuring force data, such as peak force during knot tying and the final force the knot exerts on the bands. The device used in conjunction with experienced surgical skills coaches could prove a powerful tool for providing feedback to trainees, and a similar approach could be used with other low fidelity surgical simulators to improve feedback.</p>

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Submitted by Aline Batista (alinehb.ufpel@gmail.com) on 2017-03-24T19:14:01Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Desenvolvimento arquitetural para a predição intraquadro do padrão HEVC de codificação de vídeos.pdf: 11703839 bytes, checksum: b4fcaf7b13849f6ab8c064bbe056ca11 (MD5) / Approved for entry into archive by Aline Batista (alinehb.ufpel@gmail.com) on 2017-04-05T19:13:18Z (GMT) No. of bitstreams: 2 Desenvolvimento arquitetural para a predição intraquadro do padrão HEVC de codificação de vídeos.pdf: 11703839 bytes, checksum: b4fcaf7b13849f6ab8c064bbe056ca11 (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) / Made available in DSpace on 2017-04-05T19:13:26Z (GMT). No. of bitstreams: 2 Desenvolvimento arquitetural para a predição intraquadro do padrão HEVC de codificação de vídeos.pdf: 11703839 bytes, checksum: b4fcaf7b13849f6ab8c064bbe056ca11 (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Previous issue date: 2017-02-13 / Sem bolsa / A codificação de vídeo é uma área essencial atualmente devido ao crescente aumento do número de aplicações e dispositivos eletrônicos capazes de manipular vídeos digitais de alta resolução. Com o aumento da diversidade de aplicações e com o surgimento de resoluções muito grandes como UHD 4K (3840x2160 pixels) e UHD 8K (7680x4320 pixels), foi concebido o padrão HEVC, o mais recente padrão de codificação de vídeo elaborado pelos grupos ITU-T VCEG e ISO/IEC MPEG. O HEVC é capaz de atingir as mais elevadas taxas de compressão e qualidade visual dentre todos os padrões já desenvolvidos por estes grupos. Nos padrões de codificação de vídeo, a predição intraquadro é o módulo responsável por reduzir a redundância espacial entre amostras vizinhas dentro de um mesmo quadro. O padrão HEVC define diversas novas técnicas para a predição intraquadro, tornando-a muito mais eficiente e complexa. Esta dissertação apresenta o desenvolvimento arquitetural de soluções para o módulo de predição intraquadro do padrão HEVC com diferentes objetivos de taxa de processamento, qualidade de compressão, custo em área e dissipação de potência. Todas arquiteturas desenvolvidas foram descritas em VHDL e sintetizadas para tecnologia NanGate 45 nm 0,95 v. Os resultados mostram que as arquiteturas atingem seus diferentes objetivos individuais de utilização de recursos de hardware, dissipação de potência, eficiência energética, taxa de processamento e eficiência de compressão. A principal solução proposta utiliza 4952K gates e, quando operando em uma frequência de 529 MHz, é capaz de processar vídeos UHD 8K em uma taxa de 120 quadros por segundo, com uma dissipação de 363 mW de potência e com uma eficiência energética de 32,02 pJ/amostra. Quando comparadas aos trabalhos relacionados, as soluções propostas apresentam resultados satisfatórios e competitivos. / Video coding is an essential area due to the increasing number of applications and devices that are able to handle high definition digital videos. The HEVC is the most recent and most efficient video coding standard created by the ITU-T VCEG and ISO/IEC MPEG groups, and its development was motivated by the increasing diversity of services and the emergence of beyond-HD formats such as UHD 4K (3840x2160 pixels) and UHD 8K (7680x4320 pixels). The intrapicture prediction is responsible to reduce spatial redundancy between samples inside the same frame. The HEVC standard defines several new techniques, which increase the intra prediction efficiency, but also increase its complexity. This work presents the development of hardware architectures for the HEVC intra prediction, considering different targets of compression efficiency, throughput, area cost, power dissipation and energetic efficiency. All designs were described in VHDL and synthesized using the NanGate 45 nm 0.95 v cell library. The main solution uses 4952K gates and, when running at a frequency of 529 MHz, it is able to process UHD 8K videos at 120 frames per second with a power dissipation of 363 mW and an energetic efficiency of 32.02 pJ/sample. When compared to related works, the developed architectures presented very competitive results.

abstract: Unmanned aerial vehicles (UAVs) are widely used in many applications because of their small size, great mobility and hover performance. This has been a consequence of the fast development of electronics, cheap lightweight flight controllers for accurate positioning and cameras. This thesis describes modeling, control and design of an oblique-cross-quadcopter platform for indoor-environments. One contribution of the work was the design of a new printed-circuit-board (PCB) flight controller (called MARK3). Key features/capabilities are as follows: (1) a Teensy 3.2 microcontroller with 168MHz overclock –used for communications, full-state estimation and inner-outer loop hierarchical rate-angle-speed-position control, (2) an on-board MEMS inertial-measurement-unit (IMU) which includes an LSM303D (3DOF-accelerometer and magnetometer), an L3GD20 (3DOF-gyroscope) and a BMP180 (barometer) for attitude estimation (barometer/magnetometer not used), (3) 6 pulse-width-modulator (PWM) output pins supports up to 6 rotors (4) 8 PWM input pins support up to 8-channel 2.4 GHz transmitter/receiver for manual control, (5) 2 5V servo extension outputs for other requirements (e.g. gimbals), (6) 2 universal-asynchronous-receiver-transmitter (UART) serial ports - used by flight controller to process data from Xbee; can be used for accepting outer-loop position commands from NVIDIA TX2 (future work), (7) 1 I2C-serial-protocol two-wire port for additional modules (used to read data from IMU at 400 Hz), (8) a 20-pin port for Xbee telemetry module connection; permits Xbee transceiver on desktop PC to send position/attitude commands to Xbee transceiver on quadcopter. The quadcopter platform consists of the new MARK3 PCB Flight Controller, an ATG-250 carbon-fiber frame (250 mm), a DJI Snail propulsion-system (brushless-three-phase-motor, electronic-speed-controller (ESC) and propeller), an HTC VIVE Tracker and RadioLink R9DS 9-Channel 2.4GHz Receiver. This platform is completely compatible with the HTC VIVE Tracking System (HVTS) which has 7ms latency, submillimeter accuracy and a much lower price compared to other millimeter-level tracking systems. The thesis describes nonlinear and linear modeling of the quadcopter’s 6DOF rigid-body dynamics and brushless-motor-actuator dynamics. These are used for hierarchical-classical-control-law development near hover. The HVTS was used to demonstrate precision hover-control and path-following. Simulation and measured flight-data are shown to be similar. This work provides a foundation for future precision multi-quadcopter formation-flight-control. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2018

In this study, a P300 based Brain-Computer Interface (BCI) system design is realized by the implementation of the Spelling Paradigm. The main challenge in these systems is to improve the speed of the prediction mechanisms by the application of different signal processing and pattern classification techniques in BCI problems. The thesis study includes the design and implementation of a 10 channel Electroencephalographic (EEG) data acquisition system to be practically used in BCI applications. The electrical measurements are realized with active electrodes for continuous EEG recording. The data is transferred via USB so that the device can be operated by any computer. v Wiener filtering is applied to P300 Speller as a signal enhancement tool for the first time in the literature. With this method, the optimum temporal frequency bands for user specific P300 responses are determined. The classification of the responses is performed by using Support Vector Machines (SVM&rsquo / s) and Bayesian decision. These methods are independently applied to the row-column intensification groups of P300 speller to observe the differences in human perception to these two visual stimulation types. It is observed from the investigated datasets that the prediction accuracies in these two groups are different for each subject even for optimum classification parameters. Furthermore, in these datasets, the classification accuracy was improved when the signals are preprocessed with Wiener filtering. With this method, the test characters are predicted with 100% accuracy in 4 trial repetitions in P300 Speller dataset of BCI Competition II. Besides, only 8 trials are needed to predict the target character with the designed BCI system.

ELECTROCHEMICAL IMPEDANCE SPECTROSCOPY (EIS) has been widely used to study the electrical properties of biological material due to its non-invasive nature and experimental reliability. However, most of the precision impedance analyzers used in EIS only provide single- or two-channel measurements which are inadequate for larger-scale multiplexed measurements, such as those found in modern microfluidic cell culture experiments. The Biomedical Microsystems Laboratory has developed a 16-channel cell culture platform with integrated electrode arrays for monitoring cell growth and electrical properties (i.e., the so-called “electrical phenotype”). In this paper, a system consisting of a 16-channel solid-state analog multiplexer (MUX)paired with a low-cost, impedance analyzer is developed to replace high-cost physical relay MUX and impedance analyzer systems. System requirements and design constraints for monitoring biological systems are considered and a prototype device was fabricated. Initial testing was performed on a breadboard to verify the feasibility of the design idea. Results identified measurement errors due to parasitic elements in the system. Software compensation successfully corrected for parasitic capacitance in the analog MUX design. The accuracy of the measurement system was evaluated on a developed Printed Circuit Board Assembly (PCBA) by comparing theoretical values to MUX compensated data. Finally, an EIS experiment was carried out with tap water with the PCBA system, and measurement results were analyzed using an equivalent Circuit Model (ECM). These results successfully captured the dynamics of charge transport in the electrical double layer, consistent with a modified-Randlecell ECM.