This thesis considers the problem of designing gain scheduled flight control system (FCS) for large transport aircraft that satisfy handling qualities criteria. The goal is to design a set of local Linear Time Invariant (LTI) controllers to cover the wide non- linear aircraft operation flight envelope from the viewpoint of the handling qualities assessment. The global gain scheduler is then designed that interpolates between the gains of the local controllers in order to transfer smoothly between different equilibrium points, and more importantly to satisfy the handling qualities over the entire flight envelope. The mathematical model of the Boeing 747-100/200 aircraft is selected for the purpose of the flight controller design and handling qualities as- sessment. In order to achieve an attitude hold characteristic, and also improve the dynamic tracking behavior of the aircraft, longitudinal pitch Rate Command-Attitude Hold (RCAH) controllers are designed as the local flight controllers at the specific equilib- rium points in the flight envelope by means of a state space pole placement design procedure. The handling qualities assessment of the aircraft is presented, based on which the scheduler is designed. A number of existing criteria are employed to assess the han- dling qualities of the aircraft, including the Control Anticipation Parameter (CAP), Neal and Smith, and C∗ criteria. The gain scheduled flight controller is found to have satisfactory handling qualities. The global gain scheduler is designed by interpolating the gains of the local flight controllers in order to transfer smoothly between different equilibrium points, and more importantly to satisfy the handling qualities over the flight envelope. The main contribution of this research is the combination of the gain scheduling technique based on the local controller design approach and handling qualities as- sessment. The controllers are designed based at a number of operating points and the interpolation between them (scheduling) takes place through the scheduling scheme functions. The aircraft augmented with gain-scheduled controller performs satisfactorily and meets the requirement of handling qualities. Moreover, the per- formance using the gain-scheduled controller is considerably improved compared to the performance using the fixed one.

The Canadian canola breeding sector met a transition from publicly funded breeding research to large private investments in research and development (R&D). The increasing use of biotechnology tools in the mid 1990s made the assignment of plant ownership technically possible while the legislative safeguards that were put in place during the same period enabled owners to take juristic actions against potential infringers. Today, canola breeding sector is dominated by large multinational firms. The generation of proprietary knowledge in the canola breeding sector has caused a freedom to operate issue. Private and public firms conducting canola R&D are seriously concerned about their ability to gain and preserve access to key technologies in an IPR world. <p>This thesis uses the tragedy of the anticommons framework to analyze the consequences of increased intellectual property protection in the canola breeding sector. Theory suggests that when a common resource is owned by multiple owners, each of the owners has the incentive to overcharge potential users, leading to the underuse of the resource. In R&D, different owners of complementary technologies may overcharge potential R&D firms that want to assemble different technological pieces to produce a new one. The result is forgoing research and development of new products.<p>The results of personal interviews with thirteen canola researchers and IP officers are presented and analyzed. The results suggest that the increase in the intellectual property protection in the last two decades in the canola breeding sector has led to difficulties with canola R&D. These difficulties take the form of reduced access to current, proprietary and public material. With hampered access to research input material, research output is not maximized and potential research may be forgone. Interviewees described how the increase in the intellectual property protection affects their personal and organizations ability to conduct research as well as some the implications of the new IP regime on the canola breeding sector. There is indication that canola breeding sector is moving towards a super-protectionism. Under these conditions, canola R&D firms, private and public, are in search for ways that will open access to enabling technologies and research areas. The creation of platform technologies and collaborations are the most prominent ones and are observed to increase in occurrence world wide.

ABSTRACT EFFECTS OF VERTICAL EXCITATION ON SEISMIC PERFORMANCE OF HIGHWAY BRIDGES AND HOLD-DOWN DEVICE REQUIREMENT Domani&ccedil / , Kemal Arman M.S., Department of Civil Engineering Supervisor: Assist. Prof. Dr. Alp Caner February 2008, 152 pages Most bridge specifications ignore the contribution of vertical motion in earthquake analyses. However, vertical excitation can develop significant damage, especially at bearing locations as indeed was the case in the recent 1999 izmit Earthquake. These observations, combined with recent developments in the same direction, supplied the motivation to investigate the effects of vertical component of strong ground motion on standard highway bridges in this study. Reliability checks of hold-down device requirements per AASHTO Bridge Specifications have been conducted in this context. Six spectrum compatible accelerograms were generated and time history analyses were performed to observe the uplift at bearings. Selected case studies included precast pre-stressed I-girders with concrete slab, composite steel I-girders, post-tensioned concrete box section, and composite double steel box section. According to AASHTO specifications, hold-down devices were required in two cases, for which actual forces obtained from time history analyses have been compared with those suggested per AASHTO. The only non-linearity introduced to the analyses was at the bearing level. A discussion of effects on substructure response as well as compressive bearing forces resulting from vertical excitation is also included. The results of the study confirmed that the provisions of AASHTO governing hold-down devices are essential and reasonably accurate. On the other hand, they might be interpreted as well to be suggesting that vertical ground motion components could also be included in the load combinations supplied by AASHTO, especially to be able to estimate pier axial forces and cap beam moments accurately under combined vertical and horizontal excitations.

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

The objective of this research is to explore high-speed analog-to-digital converters (ADCs) using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for wireless digital receiver applications. The stringent requirements of ADCs for the high-performance next-generation wireless digital receiver include (1) low power, (2) low cost, (3) wide input signal bandwidth, (4) high sampling rate, and (5) medium to high resolution. The proposed research achieves the objective by implementing high-performance ADC's key building blocks and integrating these building blocks into a complete sigma-delta analog-to-digital modulator that satisfies the demanding specifications of next-generation wireless digital receiver applications. The scope of this research is divided into two main parts: (1) high-performance key building blocks of the ADC, and (2) high-speed sigma-delta analog-to-digital modulator. The research on ADC's building blocks includes the design of two high-speed track-and-hold amplifiers (THA) and two wide-bandwidth comparators operating at the sampling rate > 10 GS/sec with satisfying resolution. The research on high-speed sigma-delta analog-to-digital modulator includes the design and experimental characterization of a high-speed second-order low-pass sigma-delta modulator, which can operate with a sampling rate up to 20 GS/sec and with a medium resolution. The research is envisioned to demonstrate that the SiGe HBT technology is an ideal platform for the design of high-speed ADCs.

Universiẗat, Diss.--Köln, 2003.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.