<p>U doktorskoj disertaciji su prikazani elektronski sistemi razvijeni za<br />obradu signala sa senzora promenjive izlazne impedanse, koji se mogu<br />koristiti za različite vrste senzora. Razvijen je prototip mernog sistema<br />pomoću diskretnih komponenti. Merenja izvedena na ovom prototipu dokazala<br />su da se sa izabranom mernom metodom mogu dobiti zadovoljavajući rezultati<br />merenja. Projektovanjem analognog dela elektronskog sistema u CMOS<br />tehnologiji smanjene su dimenzije i potrošnja elektronskog sistema za obradu<br />signala, a poboljšane su merne karakteristike u odnosu na izvedu u<br />diskretnoj tehnologiji.</p> / <p>In this thesis, an electronic system for signal processing of sensors with variable<br />impedance has been developed. It can be used with different types of sensors. A<br />prototype of electronic system has been developed using discrete components.<br />Measurements made with this prototype have proved that applied measurement<br />method can be used to obtain satisfying measurement results. By designing analog<br />parts of electronic system in CMOS technology, dimensions and power consumption<br />of the electronic system for signal processing and measurement characteristics have<br />been improved, comparing to the prototype developed using discrete components.</p>

Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design and simulation of a ring oscillator that exhibits the frequency modulated signal on a single integrated circuit chip. The ring oscillator is controlled by a voltage ramp signal generator and a voltage to current (V-I) converter. The circuit is designed in Cadence using TSMC 180nm process technology and operates in the frequency range of 3.409 GHz to 5.349 GHz with a spectral bandwidth of 1.94 GHz, which meets the Federal Communications Commission’s standards for unlicensed ultra-wideband transmissions.

台灣的IC設計產業總產值全球僅次於美國，自從九零年代中期成為我國極受矚目的產業。因此本研究所探討的主題為全球IC設計產業的生產效率分析，以2003年全球營收前卅大IC設計廠商為樣本。透過資料包絡法(Data Envelopment Analysis，DEA)，針對不同地區與個別廠商進行2000年至2002年的效率分析，最後進行Tobit迴歸分析，求得影響廠商生產績效的因子，提供本國廠商改善效率的參考，實證結果為： 1.DEA跨國比較的結果顯示，在2000年至2002年整體技術效率值最高的地區為美國，在2000年與2001年為台灣整體技術效率值僅次於美國，但在2002年卻落居第三。觀察個別廠商績效，Qualcomm、MediaTek、Marvell、ICS、Lattice、Pmc-Sierra與DSP Group等廠商績效最好，其整體技術效率值為1。 2.Malmquist生產力指數(MPI)跨國比較的結果顯示，臺、美、加三國總要素生產力均呈現退步的情形，2001至2002年，臺、加總要素生產力呈現進步，美國呈現退步。就個別廠商而言，在2000年至2001年間有四家廠商總要素生產力進步，在2001至2002年年則有十五家廠商總要素生產力呈現進步的狀況。 3.Tobit迴歸分析的結論為：存貨週轉率inventory turnover對整體技術效率有顯著的正向影響；負債比率與平均收帳期間均對整體技術效率有顯著的負面影響。研發費用率、經營年限與整體技術效率呈現正向關係，至於每人配備率則呈現負相關。 / The total output value of Taiwanese IC design industry is the globally second following United States. It had become the domestic gazed industry since mid 90s. Therefore, this research studies the production efficiency of global IC design industry and chooses the firms which sales globally ranked top 30 as samples. Through DEA, this thesis analyzes the efficiency focused on different regions and individual firms from 2000 to 2002. And finally, the Tobit regression model is proposed to find out the factors that influenced performances of firms and it could be reference for the domestic firms to improve their production efficiency and productivity. The results display: 1. By comparison with regions, the DEA results display that U.S.A. United States has the highest overall technical efficiency(TE) value during 2000 to 2002. Taiwan ranked behind U.S. both in 2000 and 2001 but dropped to the 3rd position in 2003. Observing performances of individual firms, Qualcomm, MediaTek, Marvell, ICS, Lattice, Pmc-Sierra and DSP Group performed as the best and their efficiency value is 1. 2. By comparison with regions, Malmquist Productivity Index(MPI) results display that the U.S.., Taiwan and Canada showed their Total Factors Productivity (TFP) to degenerate from 2000 to 2001. However, Taiwan and Canada showed their progressive TFP, progress in TFP but U.S.A. had a regressive TFP from 2001 to 2002. For one individual firm, there were only 4 firms’ TFP being aggressive from 2000 to 2001 and there are 15 firms’ TFP aggressive from 2001 to 2002. 3. The result from running Tobit regression models display that Inventory Turnover has significant positive effect to TE; Debate Ratio and Average Collection Period have significant negative effect to TE; R&D Ratio and Incorporated Period have direct relation with TFE and Equipment Per Employee has negative relation with TE.

本研究是第一篇針對台灣IC設計業的研發活動進行效率分析的論文。文中對研發的投入及產出變數作深入的探討，不僅以研發資本而非研發費用及加權研發人力為投入並且加入公司知識累積存量的概念。其中自有知識存量以自有公司前期累積專利申請數為替代變數。而產出部分也不僅考慮當年申請專利數核准數量還包括下一年度營業毛利。使用兩階段資料包絡分析法探討研發投入的運用效率。第一階段使用投入導向DEA-CCR與DEA-BCC模式評估2000年到2002年台灣上市上櫃IC設計業者運用研發資源能力所得出的研發效率值並作差額變數分析，第二階段採用Tobit迴歸分析尋找可能影響研發整體效率影響因子。最後，本研究依據研究結果提出對管理者及未來研究給予建議。 實證結果發現，〈聯發科〉是連續三年被評估相對整體效率為1的廠商，〈威盛〉與〈立錡〉為表現其次的廠商。就整體產業而言，三年的研發效率呈現低效率狀況，表示其研發資源有嚴重浪費與錯置的情形。效率分析中可看出研發資本（RK）對加權研發人力（RL）比值相對高的廠商，相對整體效率值呈現逐年負向趨勢。經過Tobit迴歸參數推估檢定本研究六大假說，人力素質、每人年約收入及研發人力密集度都與研發效率成正向關係。而員工平均年資與研發效率值呈現負向關係，與研究的預期關係不同。為第一線晶圓代工廠（聯電或台積電）轉投資的IC設計公司，研發效率並不因此網絡關係而有所影響。公司規模大小也不影響研發效率的表現。

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

Esse trabalho apresenta uma proposta na área de Educação em Microeletrônica que visa enriquecer práticas de ensino adotadas na área de projetos de circuitos integrados através do uso de máquinas de ensino-aprendizagem (TLM Teaching-Learning Machine) em aulas de laboratórios como instrumentos auxiliares e complementares ao ensino teórico. As TLMs propostas permitem a verificação experimental de conceitos fundamentais em VLSI Design, tais como: polarização de transistores NMOS e PMOS, inversores CMOS, curvas de transferência do inversor CMOS, implementação de diversas portas lógicas CMOS estática e dinâmica usando transistores de passagem ou portas de transmissão (NAND, NOR, AND, OR, XOR, XNOR, MUX, DECODER, Half ADDERs e Full ADDERs), Latches, Flip-flops e células de memória (RAM e ROM). A metodologia usada foi baseada em pesquisa bibliográfica, observações em sala de aula, participação em projetos didáticos, entrevistas com alunos e professores de microeletrônica. As TLMs foram construídas na forma de painéis de papelão de 100 cm x 70 cm com eletrônica embarcada ou conjuntos de módulos de circuito impresso com tamanhos A4 até A10, interligados entre si por meio de conectores, cabos elétricos padronizados e acondicionados em caixas flexíveis de borracha sintética. Considerou-se o uso combinado desses materiais com diferentes técnicas de montagens eletrônicas. No leiaute das TLMs foram considerados aspectos da interação homem-máquina (HMI) e projetos de interações por PREECE (2002), e da transposição didática de CHEVALHARD e JOSHUA (1981). Os resultados efetivos da aprendizagem usando TLMs foram obtidos por meio de uma dinâmica em sala de aula baseada no microensino em ALLEN (1967). / This paper presents a proposal in the area of Education in Microelectronics which aims to enrich the educational practices adopted in the area of integrated circuits design through the use of teaching-learning machines (TLM) in classes, laboratories as auxiliary and complementary instruments to the theoretical ones. The proposed TLMs allow the experimental verification of fundamental concepts in VLSI design, such as: NMOS and PMOS transistors biasing, CMOS inverters, transfer curves of a CMOS inverter, implementation of various static and dynamic CMOS logic using the pass-transistor or transmission gates (NAND, NOR, AND, OR, XOR, XNOR, MUX, DECODER, Half ADDERs and Full ADDERs), Latches, flip-flops and memory cells (RAM and ROM). The used methodology was based on a literature search, observations in the classroom, participation in educational projects, interview of students and professors involved with microelectronics. The TLMs were assembled in the form of paper panels, 100 cm x 70 cm embedded with electronic modules, or sets of printed circuit boards with A4 size up to A10 size, connected with each other through connectors, electrical wires and packed in synthetic rubber flexible boxes. The combined use of these materials with different techniques of electronic assemblies has been very important. The layout of TLMs concerns about the aspects of human-machine interaction (HMI) and design interactions from PREECE (2002), and the didactical transposition from CHEVALHARD and JOSHUA (1981). The effective learning results using TLMs were obtained through a dynamic in classroom based on microteaching from ALLEN (1967).

Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads.

For many years batteries have been used as the main power sources for portable electronic devices. However, the rate of scaling in integrated circuits and micro-electro-mechanical systems (MEMS) has been much higher than that of the batteries technology. Therefore, a need to replace these temporary energy reservoirs with small sized continuously charged energy supply units has emerged. These units, named as energy harvesters, use several types of ambient energy sources such as heat, light, and vibration to provide energy to intelligent systems such as sensor nodes. Among the available types, vibration based electromagnetic (EM) energy harvesters are particularly interesting because of their simple structure and suitability for operation at low frequency values (&lt / 10 Hz), where most vibrations exits. However, since the generated EM power and voltage is relatively low at low frequencies, high performance interface electronics is required for efficiently transferring the generated power from the harvester to the load to be supplied. The aim of this study is to design low power and efficient interface electronics to convert the low voltage and low power generated signals of the EM energy harvesters to DC to be usable by a real application. The most critical part of such interface electronics is the AC/DC converter, since all the other blocks such as DC/DC converters, power managements units, etc. rely on the rectified voltage generated by this block. Due to this, several state-of-the-art rectifier structures suitable for energy harvesting applications have been studied. Most of the previously proposed rectifiers have low conversion efficiency due to the high voltage drop across the utilized diodes. In this study, two rectifier structures are proposed: one is a new passive rectifier using the Boot Strapping technique for reducing the diode turn-on voltage values / the other structure is a comparator-based ultra low power active rectifier. The proposed structures and some of the previously reported designs have been implemented in X-FAB 0.35 &micro / m standard CMOS process. The autonomous energy harvesting systems are then realized by integrating the developed ASICs and the previously proposed EM energy harvester modules developed in our research group, and these systems have been characterized under different electromechanical excitation conditions. In this thesis, five different systems utilizing different circuits and energy harvesting modules have been presented. Among these, the system utilizing the novel Boot Strap Rectifier is implemented within a volume of 21 cm3, and delivers 1.6 V, 80 &micro / A (128 &micro / W) DC power to a load at a vibration frequency of only 2 Hz and 72 mg peak acceleration. The maximum overall power density of the system operating at 2 Hz is 6.1 &micro / W/cm3, which is the highest reported value in the literature at this operation frequency. Also, the operation of a commercially available temperature sensor using the provided power of the energy harvester has been shown. Another system utilizing the comparator-based active rectifier implemented with a volume of 16 cm3, has a dual rail output and is able to drive a 1.46 V, 37 &micro / A load with a maximum power density of 6.03 &micro / W/cm3, operating at 8 Hz. Furthermore, a signal conditioning system for EM energy harvesting has also been designed and simulated in TSMC 90 nm CMOS process. The proposed ASIC includes a highly efficient AC-DC converter as well as a power processing unit which steps up and regulates the converted DC voltages using an on-chip DC/DC converter and a sub-threshold voltage regulator with an ultra low power management unit. The total power consumption on the totally passive IC is less than 5 &micro / W, which makes it suitable for next generation MEMS-based EM energy harvesters. In the frame of this study, high efficiency CMOS rectifier ICs have been designed and tested together with several vibration based EM energy harvester modules. The results show that the best efficiency and power density values have been achieved with the proposed energy harvesting systems, within the low frequency range, to the best of our knowledge. It is also shown that further improvement of the results is possible with the utilization of a more advanced CMOS technology.

Αντικείμενο της παρούσας Ειδικής Επιστημονικής Εργασίας είναι η μελέτη, σχεδίαση, εξομοίωση και φυσική σχεδίαση ενός αναλογικού μιγαδικού ζωνοδιαβατού φίλτρου 6ης τάξης. Βασικές δομικές μονάδες του φίλτρου είναι ενισχυτές ρεύματος οι οποίοι χρησιμοποιούν τη βαθμίδα “Flipped Voltage Follower”. Με τη συγκεκριμένη βαθμίδα είναι εφικτή η σχεδίαση όλων των επιμέρους κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας-χαμηλής κατανάλωσης ισχύος. / The subject of this master thesis is the design, simulation and physical layout of a 6th order analog complex bandpass filter. The filter is constructed by current mirrors which are utilizing the cell "Fliped Voltage Follower". Thus, all of the circuits offer the benefit of operating in low-voltage/low-power environment.

Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device are more prone to these unaccounted-for changes. To achieve a robust design, the random and systematic fluctuations in the manufacturing process and the variations in the environmental parameters should be analyzed and the impact on the parametric yield should be addressed. This thesis studies the challenges and comprises solutions for designing robust VLSI systems in the presence of variations. Initially, to get some insight into the system design under variability, the parametric yield is examined for a small circuit. Understanding the impact of variations on the yield at the circuit level is vital to accurately estimate and optimize the yield at the system granularity. Motivated by the observations and results, found at the circuit level, statistical analyses are performed, and solutions are proposed, at the system level of abstraction, to reduce the impact of the variations and increase the parametric yield. At the circuit level, the impact of the supply and threshold voltage variations on the parametric yield is discussed. Here, a design centering methodology is proposed to maximize the parametric yield and optimize the power-performance trade-off under variations. In addition, the scaling trend in the yield loss is studied. Also, some considerations for design centering in the current and future CMOS technologies are explored. The investigation, at the circuit level, suggests that the operating temperature significantly affects the parametric yield. In addition, the yield is very sensitive to the magnitude of the variations in supply and threshold voltage. Therefore, the spatial variations in process and environmental variations make it necessary to analyze the yield at a higher granularity. Here, temperature and voltage variations are mapped across the chip to accurately estimate the yield loss at the system level. At the system level, initially the impact of process-induced temperature variations on the power grid design is analyzed. Also, an efficient verification method is provided that ensures the robustness of the power grid in the presence of variations. Then, a statistical analysis of the timing yield is conducted, by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This ensures an accurate estimation of the timing yield. In addition, a method is proposed to accurately estimate the power yield considering process-induced temperature and supply voltage variations. This helps check the robustness of the circuits early in the design process. Lastly, design solutions are presented to reduce the power consumption and increase the timing yield under the variations. In the first solution, a guideline for floorplaning optimization in the presence of temperature variations is offered. Non-uniformity in the thermal profiles of integrated circuits is an issue that impacts the parametric yield and threatens chip reliability. Therefore, the correlation between the total power consumption and the temperature variations across a chip is examined. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. The second design solution provides an optimization methodology for assigning the power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming (MINLP) optimization problem, subject to voltage drop and current constraint, is efficiently solved to find the optimum number and location of the pads.