ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

ASICs estruturados com leiautes regulares representam uma das soluções para a perda de rendimento de fabricação de circuitos integrados em tecnologias nanométricas causada pela distorção de fotolitografia. Um método de projeto de circuitos integrados ainda mais restritivo resulta em ASICs estruturados configuráveis apenas pelas camadas de vias, que são compostos pela repetição do mesmo modelo de bloco em todas as camadas do leiaute, exceto as camadas de vias. A escolha do modelo de bloco tem grande influência nas características do circuito final, criando a demanda por novas ferramentas de CAD que possam avaliar e comparar tais modelos em seus diversos aspectos. Esta tese descreve um ambiente de CAD baseado em SAT, capaz de avaliar o aspecto de capacidade lógica em padrões de blocos configuráveis por vias. O ambiente proposto é genérico, podendo tratar quaisquer padrões de bloco definido pelo usuário, e se comporta de maneira eficiente quando aplicado aos principais padrões já publicados na literatura. / Structured ASICs with regular layouts comprise a design-based solution for IC manufacturing yield loss in nanometer technologies caused by photolithography distortions. Via-configurable structured ASICs is even a more restrictive digital IC design method, based on the repetition of a block template comprising all layout layers except the vias one. The choice of such a design strategy impacts greatly the final circuit characteristics, arising the need for specific CAD tools to allow template evaluation and comparison in different aspects. This work presents a SAT-based CAD environment for evaluating the logical capacity aspect of via-configurable block templates. The proposed environment is able to support any user-defined template, and behaves efficiently when applied to block templates presented in related literature.

Esse trabalho apresenta uma proposta na área de Educação em Microeletrônica que visa enriquecer práticas de ensino adotadas na área de projetos de circuitos integrados através do uso de máquinas de ensino-aprendizagem (TLM Teaching-Learning Machine) em aulas de laboratórios como instrumentos auxiliares e complementares ao ensino teórico. As TLMs propostas permitem a verificação experimental de conceitos fundamentais em VLSI Design, tais como: polarização de transistores NMOS e PMOS, inversores CMOS, curvas de transferência do inversor CMOS, implementação de diversas portas lógicas CMOS estática e dinâmica usando transistores de passagem ou portas de transmissão (NAND, NOR, AND, OR, XOR, XNOR, MUX, DECODER, Half ADDERs e Full ADDERs), Latches, Flip-flops e células de memória (RAM e ROM). A metodologia usada foi baseada em pesquisa bibliográfica, observações em sala de aula, participação em projetos didáticos, entrevistas com alunos e professores de microeletrônica. As TLMs foram construídas na forma de painéis de papelão de 100 cm x 70 cm com eletrônica embarcada ou conjuntos de módulos de circuito impresso com tamanhos A4 até A10, interligados entre si por meio de conectores, cabos elétricos padronizados e acondicionados em caixas flexíveis de borracha sintética. Considerou-se o uso combinado desses materiais com diferentes técnicas de montagens eletrônicas. No leiaute das TLMs foram considerados aspectos da interação homem-máquina (HMI) e projetos de interações por PREECE (2002), e da transposição didática de CHEVALHARD e JOSHUA (1981). Os resultados efetivos da aprendizagem usando TLMs foram obtidos por meio de uma dinâmica em sala de aula baseada no microensino em ALLEN (1967). / This paper presents a proposal in the area of Education in Microelectronics which aims to enrich the educational practices adopted in the area of integrated circuits design through the use of teaching-learning machines (TLM) in classes, laboratories as auxiliary and complementary instruments to the theoretical ones. The proposed TLMs allow the experimental verification of fundamental concepts in VLSI design, such as: NMOS and PMOS transistors biasing, CMOS inverters, transfer curves of a CMOS inverter, implementation of various static and dynamic CMOS logic using the pass-transistor or transmission gates (NAND, NOR, AND, OR, XOR, XNOR, MUX, DECODER, Half ADDERs and Full ADDERs), Latches, flip-flops and memory cells (RAM and ROM). The used methodology was based on a literature search, observations in the classroom, participation in educational projects, interview of students and professors involved with microelectronics. The TLMs were assembled in the form of paper panels, 100 cm x 70 cm embedded with electronic modules, or sets of printed circuit boards with A4 size up to A10 size, connected with each other through connectors, electrical wires and packed in synthetic rubber flexible boxes. The combined use of these materials with different techniques of electronic assemblies has been very important. The layout of TLMs concerns about the aspects of human-machine interaction (HMI) and design interactions from PREECE (2002), and the didactical transposition from CHEVALHARD and JOSHUA (1981). The effective learning results using TLMs were obtained through a dynamic in classroom based on microteaching from ALLEN (1967).

<div>The design of advanced integrated circuits (ICs) and systems calls for multiphysics and large-scale modeling and simulation methods. On the one hand, novel devices and materials are emerging in next-generation IC technology, which requires multiphysics modeling and simulation. On the other hand, the ever-increasing complexity of ICs requires more efficient numerical solvers.</div><div><br></div><div>In this work, we propose a multiphysics modeling and simulation algorithm to co-simulate Maxwell's equations, dispersion relation of materials, and Boltzmann equation to characterize emerging new devices in IC technology such as Cu-Graphene (Cu-G) hybrid nano-interconnects. We also develop an unconditionally stable time marching scheme to remove the dependence of time step on space step for an efficient simulation of the multiscaled and multiphysics system. Extensive numerical experiments and comparisons with measurements have validated the accuracy and efficiency of the proposed algorithm. Compared to simplified steady-state-models based analysis, a significant difference is observed when the frequency is high or/and the dimension of the Cu-G structure is small, which necessitates our proposed multiphysics modeling and simulation for the design of advanced Cu-G interconnects. </div><div><br></div><div>To address the large-scale simulation challenge, we develop a new split-field domain-decomposition algorithm amenable for parallelization for solving Maxwell’s equations, which minimizes the communication between subdomains, while having a fast convergence of the global solution. Meanwhile, the algorithm is unconditionally stable in time domain. In this algorithm, unlike prevailing domain decomposition methods that treat the interface unknown as a whole and let it be shared across subdomains, we partition the interface unknown into multiple components, and solve each of them from one subdomain. In this way, we transform the original coupled system to fully decoupled subsystems to solve. Only one addition (communication) of the interface unknown needs to be performed after the computation in each subdomain is finished at each time step. More importantly, the algorithm has a fast convergence and permits the use of a large time step irrespective of space step. Numerical experiments on large-scale on-chip and package layout analysis have demonstrated the capability of the new domain decomposition algorithm. </div><div><br></div><div>To tackle the challenge of efficient simulation of irregular structures, in the last part of the thesis, we develop a method for the stability analysis of unsymmetrical numerical systems in time domain. An unsymmetrical system is traditionally avoided in numerical formulation since a traditional explicit simulation is absolutely unstable, and how to control the stability is unknown. However, an unsymmetrical system is frequently encountered in modeling and simulating of unstructured meshes and nonreciprocal electromagnetic and circuit devices. In our method, we reduce stability analysis of a large system into the analysis of dissembled single element, therefore provides a feasible way to control the stability of large-scale systems regardless of whether the system is symmetrical or unsymmetrical. We then apply the proposed method to prove and control the stability of an unsymmetrical matrix-free method that solves Maxwell’s equations in general unstructured meshes while not requiring a matrix solution.<br></div><div><br></div>

<p>Nisko-šumni pojačavač (NŠP) nalazi se u prijemnom delu bežičnog<br />primopredajnika neposredno nakon antene. NJegova uloga je da ulazni<br />signal određene frekvencije i male snage izdvoji i pojača iznad nivoa<br />šuma prijemnika. U okviru doktorske disertacije prikazane su i<br />opisane metode za projektovanje širokopojasnih (UWB) NŠP u CMOS<br />tehnologiji. Ukupno je predloženo devet novih konfiguracija NŠP. Na<br />osnovu dobijenih rezultata, u 0,18 &mu;m UMC CMOS tehnologiji<br />realizovan je i fabrikovan NŠP jednostavne topologije, koja<br />predstavlja zbir dva pristupa, pojačavačkog stepena kaskodne<br />strukture sa povratnom spregom i stepena sa višestrukim<br />iskorišćenjem struje. NŠP je projektovan za frekvencijski opseg od<br />3,1 do 5 GHz. Takođe, opisana je metoda za merenje parametara NŠP, a<br />zatim je i izvršena njegova karakterizacija.</p> / <p>In the transceiver chain the low noise amplifier (LNA) is placed in the frontend<br />of the receiver after the antenna. The LNA needs to isolate and amplify<br />received weak signal at a specific frequency above the noise level of the<br />receiver. In the scope of this doctoral dissertation methods for designing<br />ultra-wideband (UWB) LNA in CMOS technology are presented and<br />described. Nine new LNA configurations were proposed. Based on the<br />obtained results, simple LNA configuration, obtained by merging casode<br />feedback topology and current-reuse technique, was realized and fabricated<br />in 0.18 &mu;m UMC CMOS technology. The LNA is designed for the frequency<br />band from 3.1 to 5 GHz. In addition, the method for measurement LNA<br />parameters is described and the proposed LNA was characterized.</p>

No description available.

Οι εφαρμογές της σύγχρονης τεχνολογίας επιτάσσουν τη χρήση συσκευών με όσο το δυνατόν μικρότερες διαστάσεις, χαμηλή τάση τροφοδοσίας, χαμηλή κατανάλωση ισχύος και ταυτόχρονα υψηλές επιδόσεις. Το αντικείμενο της εργασίας αυτής, αφορά στη σχεδίαση αναλογικών ολοκληρωμένων φίλτρων, χαμηλής τάσης τροφοδοσίας, για υλοποίηση μεγάλων σταθερών χρόνου, στο πεδίο του λογαρίθμου. Προς αυτή την κατεύθυνση, μελετώντας και σχεδιάζοντας δομές αναλογικών φίλτρων στο πεδίο του λογαρίθμου, επιτεύχθηκε η σχεδίαση φίλτρων δεύτερης τάξης με μεγάλες σταθερές χρόνου, διατηρώντας τις φυσικές διαστάσεις των κυκλωμάτων σε εξαιρετικά χαμηλά επίπεδα. Αρχικά, παρουσιάζονται κάποια εισαγωγικά στοιχεία για την σχεδίαση ολοκληρωμένων κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας. Γίνεται εισαγωγή στην ιδέα των λογαριθμικών φίλτρων και αναλύονται οι βασικές αρχές σχεδίασης. Παρουσιάζονται βασικά χαρακτηριστικά των κυκλωμάτων στο πεδίο του λογαρίθμου, καθώς και ανάλυση των τελεστών και των διαγωγών που αποτελούν τη βάση της σχεδίασης στο λογαριθμικό πεδίο. Επιπλέον, παρουσιάζονται οι υλοποιήσεις των ολοκληρωτών των φίλτρων στο πεδίο του λογαρίθμου. Στη συνέχεια, γίνεται τοπολογική εξομοίωση 2ης τάξης βαθυπερατών φίλτρων στο πεδίο του λογαρίθμου. Σχεδιάζονται φίλτρα με την κλασική μέθοδο υλοποίησης, κάνοντας χρήση ισοδύναμων των παθητικών στοιχείων στο λογαριθμικό πεδίο, αλλά και φίλτρα υλοποιημένα με διάγραμμα ροής (SFG). Παρουσιάζονται τα πρώτα αποτελέσματα των εξομοιώσεων που πραγματοποιήθηκαν με το λογισμικό Cadence και το γραφικό περιβάλλον που διαθέτει για την σχεδίαση αναλογικών ηλεκτρονικών κυκλωμάτων (Virtuoso Analog Environment). Προτείνονται, δύο κυκλώματα τα οποία πραγματοποιούν πολλαπλασιασμό της χωρητικότητας των πυκνωτών, επιτυγχάνοντας έτσι μεγάλες σταθερές χρόνου, και η υλοποίηση νέων ολοκληρωτών που κάνουν χρήση των πολλαπλασιαστών. Δημιουργούνται έτσι οι βάσεις για την υλοποίηση φίλτρων με εξαιρετικά μικρές διαστάσεις, των οποίων η σχεδίαση, η εξομοίωση και η φυσική σχεδίαση (layout design) παρουσιάζονται, αναλύονται και συγκρίνονται. / The technological evolution and market requirements have led to an increasing demand of low - power portable devices, featuring the reduced size of the devises and high efficiency. This M.Sc project deals with the design of analog integrated, Log - Domain filters, for low - voltage implementation, with large time - constants. In this direction, the design of a second order, low - pass filter, with the above features, and with the occupied silicon area maintained at very low levels, was achieved. In Chapters 1 and 2, an introduction to the design of integrated circuits in low voltage environment is presented. There is an introduction to the idea and the basic principles of Log - Domain filters. The key characteristics of circuits in a large signal operation point of view, and an analysis of the operators and the exponential transconductor cells are, also presented. Furthermore, the basic Log - Domain integrators has been analyzed. A topologic analysis of second order Log - Domain filters is given in Chapter 3. Filters has been initially designed firstly with the classic implementation, using Log - Domain equivalent of passive elements. In a second step, the filter has been realizes by employing the signal flow diagram (SFG) representation. These filters were simulated with the Analog Design environment of the Cadence software. the obtained simulation results confirmed the correct operation of the circuit. Two implementations for realizing the Log - Domain equivalent of a capacitor multiplier are introduced. In addition, implementations of new Log - Domain integrators, that use the capacitor multipliers, are given in Chapter 4. Using these implementations, Log - Domain filters, with reduced total area and large time - constants, are designed, simulated and characterized in Chapter 5. Finally, the layout design of a second - order has been performed in Chapter 6 and the provided post - layout simulation results show that the performance of the filter was close to that of the filter realized in schematic level.

合約訴訟管理流程主要目的是在控制及預防公司可能發生訴訟賠償的內部流程；本研究將探討合約訴訟管理流程架構及發展出適於IC設計公司之管理模式。 IC產業是台灣經濟的重要命脈亦是能在國際舞台上佔有一席之地的產業之一，IC 產業具有技術密集、高投資成本、高設備折舊、競爭激烈的產業特性，且各生產階段精細分工，上至晶圓、封裝廠乃至IC設計公司，下至組裝廠、品牌商客戶等，在這緊密合作的供應鏈關係下，合作與競爭不斷產生，在此技術掛帥的環境下，IC設計公司若沒有做好專利、商標等智慧財產權管理並做好合約審核及履行追縱之流程控管的話，IC設計公司將隨時會遭遇第三人主張侵權請求或面臨違約損害賠償之風險，故為維持IC設計公司獲利能力及在全球的競爭力，因此有效之合約訴訟管理流程將更顯其重要性。 　　本研究利用Tsaih and Lin (2006)所發展之PWIO (Process-Wide Information Organism)分析方法論來探索如何系統化地重現與評估管理流程，並以台灣-A個案IC設計公司法務中心的現行之合約訴訟管理流程為研究對象，進行：（1）重現、分析與評估該合約訴訟管理流程；（2）就流程分析結果，討論個案公司改善該合約訴訟管理流程時應重視之議題，並做成高階主管日後評估調整合約訴訟管理策略之參考；（3）發展平衡計分卡之內部流程構面的基礎，進行個案公司法務中心合約訴訟管理流程目標的描述，以及目標達成之績效衡量指標的呈現，讓策略能落實到合約訴訟管理流程，以避免及預防個案公司合約訴訟風險產生。 / The main goal of the Process of Contract Lawsuit Management (POCLM) is the process of a company that can control and prevent from arising protential lawsuit and indemnification. In this research, I will discuss the basic architecture of POCLM and develop a POCLM model applicable to the IC design company. The Integrated Circuit Industry (IC Industry) is essential economic lifeblood in Taiwan. The characteristics of the IC industry include technology-intensive, high investment cost, high equipment depreciation and intensely competitive environment. Every production process is divided into detail parts. Based on the close relationship of Supply Chain, the competition and cooperation is arising constantly. If the IC design company does not manage the intellectual property management efficiently and establish the contract reviewing and tracking process in the technology based environment, the IC design company will face the high risk of lawsuit, claim and indemnification. In order to maintain the profitability and the competitiveness of the IC design company in the world, it is more and more important to lead an effective POCLM model into the IC design company. In this research, I use the research method of PWIO (Process-Wide Information Organism) of Tsaih and Lin (2006) on a contract review process of a legal department of A IC Design Company in Taiwan, to discuss how to rebuild and evaluate the management process systematically. And I will do following studys: (1). Rebuild, analyze and evaluate the POCLM; (2). Upon the study result, provide A Design Company with a improvement suggestion of POCLM and related management issues for its director’s reference on adjusting the strategic in the future; (3). Develop the basic of Internal Business Process Perspective of Balance Scorecard (BSC), describe the goal of POCLM of the legal department of A Design Company and build the performance indicator of the goal achiving for A Design Company by BSC, to implement the strategic into the POCLM and avoid and prevent from arising any contract lawsuit against A Design Company.

La bioélectronique est un domaine interdisciplinaire qui étudie les interconnexions et les interactions entre entités biologiques (cellules, tissus, organes) et systèmes électroniques,par l’intermédiaire du transducteur adéquat. Pour des cellules ou des tissus excitables (neurones, muscles, ...), le transducteur prend la forme d’une simple électrode, car ces tissus produisent une activité électrique spontanée ou, dans le sens inverse, peuvent être excités par un signal électrique externe. Cette communication bidirectionnelle donne lieu à deux schémas expérimentaux : l’acquisition et la stimulation. L’acquisition consiste à enregistrer, traiter et analyser les bio-signaux alors que la stimulation consiste à appliquer le courant électrique adéquat aux tissus vivants, pour déclencher une réaction. Cette thèse se concentre sur ce dernier point : deux générations de système de stimulation ont été développées, chacune basée sur un circuit intégré spécifique et adaptée à différents contextes applicatifs.Tout d’abord, le cadre scientifique a été celui du projet CENAVEX, axé sur la stimulation électrique fonctionnelle pour réhabiliter la fonction respiratoire, suite à une lésion de la moelle épinière. Ensuite, les objectifs de conception ont été étendus pour couvrir de nouveaux besoins d’application : la surveillance de l’impédance électrique in situ et l’exploration des formes d’onde de stimulation originales. Le premier pourrait être une solution pour suivre la réaction tissulaire après l’implantation d’une électrode, contribuant ainsi à la biocompatibilité à long terme des implants ; le second propose d’aller au-delà dela conventionnelle impulsion biphasique carrée et d’explorer de nouvelles formes d’ondes qui pourraient être plus efficaces en termes de consommation d’énergie, pour un effet physiologique donné.Le travail présenté dans ce manuscrit contribue à la conception, à la fabrication et au test de dispositifs de stimulation innovants. Cela a conduit au développement de deux circuits intégrés et de deux dispositifs de stimulation permettant une stimulation multicanal.Les caractérisations électriques et les validations biologiques, de la faisabilité in vitro aux expériences in vivo, ont été menées et sont décrites dans ce manuscrit. / Bioelectronics is a cross-disciplinary field that studies interconnections and interactions between biological entities (cells, tissues, organs) and electronic systems, using the adequate transducer. For excitable cells or tissues (neurons, muscles, . . . ), the transducer takes the form of a simple electrode, as these tissues produce a spontaneous electrical activity or,in the opposite way, may be excited by an external electrical signal. This bi-directional communication gives rise to two experimental schemes: acquisition and stimulation. Acquisition consists in recording, processing and analyzing bio-signals whereas stimulation consists in applying the adequate electrical current to living tissues in order to trigger a reaction. This thesis focuses on the latter: two generations of stimulation systems have been developed, both being centered on an Application Specific Integrated Circuit, and adapted to different application contexts. First, the scientific framework was given by the CENAVEX project, focusing on Functional Electrical Stimulation to rehabilitate the respiratory function, following a Spinal Cord Injury. Then, the design objectives were extended to cover new application needs:in situ electrical impedance monitoring and exploration of original stimulation wave forms.The first one could be a solution to follow the tissue reaction after electrode implantation,hence contributing to long-term biocompatibility of implants; the second one proposes to go further the conventional constant biphasic pulse and explore new wave forms that couldbe most efficient in terms of energy consumption, for a given physiological effect.The work presented in this manuscript is a contribution to the design, fabrication and test of innovative stimulation devices. It leaded to the development of two integrated circuits and two stimulation devices permitting multichannel stimulation. Both electrical characterizations and biological validations, from in vitro feasibility to in vivo experiments, have been conducted and are described in this manuscript.

在繁忙的工商界，資訊代表一種情報、一種利器，如何掌握商情資訊，是企業界提昇競爭力的不二法門。IC設計業為一知識密集產業，有鑑於資訊流通、知識管理的重要性，IC設計公司成立公司圖書館（資料單位），以便於有效地保存資料，迅速提供資訊服務。本研究採用深度訪談與問卷調查法，以18家IC設計業公司圖書館為研究對象，目的在瞭解IC設計業公司圖書館的經營狀況，以及在公司知識管理中所扮演的角色。 本調查發現，IC設計業公司圖書館尚屬於起步階段，需協助公司進行品質管理，參與ISO9001的認證，所以主管單位為品保部門；人員編制少，多為一人圖書館，但服務對象卻涵蓋全公司、客戶與晶圓廠；公司圖書館蒐集資料的來源包含客戶、晶圓廠、研究機構以及公司的內部文件與研發資料，並為公司圖書館內的資源製作索引，以提供查詢、借閱。在知識管理的角色扮演上，目前IC設計業公司圖書館已掌握的資源為技術知識，以及公司內已經外顯化的知識，對於資訊知識與內隱知識，尚缺乏管理。 根據調查結果，提出以下五點建議，供IC設計業公司圖書館經營之參考：1.進行文件管理，協助品質認證；2.加強專利資料的蒐尋，實行專利、智慧財產權的管理；3.加入館際合作組織，彌補資源不足的現況；4.強調知識管理的理念，為IC設計公司整合圖書資訊系統；5.館員需要培養主動積極的態度，以知識管理者自居，經常與外界接觸，思考公司圖書館未來經營的方向，並爭取主管與工作同仁的支持與認同、協助蒐集資源。此外，在圖書資訊學系所課程部份，應建立建教合作的關係，重新規畫專門圖書館教育的課程，使圖書資訊學的專長，能運用在公司企業的資料管理。