This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages. We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

Ultra-Wideband ¡}UWB¡~Communication Technology is one of the potential technologies in indoor wireless communication applications. Because of the property of fine resolution of transmitted signal by UWB, it is powerful on indoor location applications. In the first place, we need to estimate the time of arrival based on the wireless location applications. Whether synchronization between the template signals and received signals affects directly the SNR of the estimator output and decreases the ranging accuracy. Because of the transmitted signal is the type of impulse radio for UWB system, it is more important on the time accuracy of the internal oscillator. In the thesis, we utilize the Delay-Locked Loop ¡}DLL¡~ structure with Self-tuning function to reduce the timing jitter in the internal oscillator. We can improve the stability in the tracking loop and utilize multipath canceller to cancel the multipath interference in the indoor environment. When reaching synchronization between the template signal and received signal by using the tracking loop, we can improve ranging accuracy and increase location precision according to the received signal.

Abstract¡G For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof¡¦s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 £gm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 £gs for a frequency jump of 80MHz.

Phase locking of external-cavity diodes laser¡]ECDL¡^ to the stabilized optical frequency combs of a femtosecond mode-locked laser. Optical frequency combs of a femtosecond mode-locked laser can be the reference standard of dual-wavelength external-cavity diode lasers (ECDLs). Frequency stabilization of two external-cavity diode laser is also demonstrated simultaneously.Suppression of the frequency fluctuation of two ECDLs from hundreds MHz to 200 Hz is demonstrated and characterized. Meanwhile, frequency tunable continuous-wave Tera-Hertz (cw THz) wave is generated and observed by photomixing of the output of two frequency stabilized ECDLS with tunable relative frequency difference on a photoconductive antennas. In our experiment, cw THz wave is demonstrated and with tuning range from 0.200 to 1.240THz and could be attribute as frequency standard of THz.

In this study we use AFM-based nanolithography technique to produce nanofeatures of the single strand DNA and LNA probe molecules which are prepared via thiolated nucleic acid self-assembled monolayers (SAMs) on gold substrates. The goal is to observe the topographic changes of the DNA film structures resulting from the formation of rigid double strand DNA when the target and probe DNAs bind together. The so-called hybridization depends strongly on the probe density on the substrate surface. To find the proper probe density for hybridization, we vary the concentration of the probe DNA and search for the optimal conditions for measuring the height changes of the nanofeatures. We also monitor the topographic changes of the DNA nanofeatures in the different target DNA concentrations as a function of time, and the binding isotherms are fitted with the Langmuir adsorption model to derive the equilibrium dissociation constant and maximum hybridization efficiency. In addition, we extend the nanoscale hybridization reaction detection to mismatched DNA:DNA and LNA:DNA hybridization, and observe that topographic change of mismatched hybridization is inconspicuous and rapidly reach equilibrium. The results reveal the apparent difference between the perfect match and mismatch conditions, and validate that this approach can be applied to differentiate the situations for both perfect match and mismatch cases, demonstrating its potentials in the gene chip technology.

Improving the identification ability of surfaced-immobilized nucleic acid probes for small size DNA or RNA targets, utilizing optical or electrochemical methods, has been the goal for the gene chip technology. This study focuses on new probe design for introducing hairpin structural features and locked nucleic acid modification. We use three kinds of probes (DNA-LN, DNA-HP and LNA-HP) to prepare recognition layers via self-assembly processes on a gold substrate, and utilize AFM-based nanolithography technique to produce nanofeatures to observe the stiffness changes of oligonucleotide chains resulting from the formation of rigid double stranded duplexes when target sequence hybridizes to the probe. We also monitor the topographic changes upon exposure to the single mismatched and non-complementary targets as a function of time. The results reveal LNA-HP probes exhibit the highest response to discriminating single-point mutation in the base sequence. In addition, we study the effects of salt concentration, reaction temperature and the small size on the hybridization efficiency.

Dissertation (Ph.D.)--Auburn University,2006. / Abstract. Vita. Includes bibliographic references (p.110-113).

Recently, there has been increasing interest within the potential user community of Global Positioning System (GPS) for high precision navigation problems such as aircraft non precision approach, river and harbor navigation, real-time or kinematic surveying. In view of more and more GPS applications, the reliability of GPS is at this issue. The Global Positioning System (GPS) is a space-based radio navigation system that provides consistent positioning, navigation, and timing services to civilian users on a continuous worldwide basis. The GPS system receiver provides exact location and time information for an unlimited number of users in all weather, day and night, anywhere in the world. The work in this thesis will mainly focuss on how to model a Mathematical expression for tracking GPS Signal using Phase Locked Loop filter receiver. Mathematical formulation of the filter are of two types: the first order and the second order loops are tested successively in order to find out a compromised on which one best provide a zero steady state error that will likely minimize noise bandwidth to tracks frequency modulated signal and returns the phase comparator characteristic to the null point. Then the Z-transform is used to build a phase-locked loop in software for digitized data. Finally, a Numerical Methods approach is developed using either MATLAB or Mathematica containing the package for Gaussian elimination to provide the exact location or the tracking of a GPS in the space for a given a coarse/acquisition (C/A) code.

Linearity enhancement, especially within the front end of a wireless receiver IC design, is highly desirable since it allows the front-end to withstand strong interferers from co-existing communication standards or other wireless radiators. We propose an interferer suppression method based on feed-forward cancellation that uses an injectionlocked oscillator (ILO) to extract the interferer from the incident spectrum. The technique is expected to be useful in environments where a strong narrowband interferer appears along with a wideband desired signal, such as ultra-wideband (UWB) and emerging cognitive-radio applications. The ILO is further embedded within a phase-locked loop which provides several advantages including ILO center frequency self tuning and automatic phase alignment between the main signal path and the auxiliary path. An IC that uses this approach is implemented in a UMC 0.18[mu]m RFCMOS process. In measurement, the chip demonstrates 20dB suppression for phase and frequency modulated interferers while maintaining around 18dB power gain and noise figure below 5dB, measured with an off-chip balun for the desired signal. Techniques for canceling amplitude modulated interferers, though not included in the integrated circuit, were also demonstrated with an off chip amplitude control loop. Over 20dB rejection was obtained with AM interferers with properly scaled envelop signal applied to the ILO bias port. A second LNA was connected in cascade with the system to emulate the input stage of a down-conversion mixer and the cascaded P1dB was improved over 16dB with cancellation on. Gain compression above 13dB was also observed when auxiliary path was disabled, at the same input level as the P1dB with cancellation applied. / text

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text