Improving the identification ability of surfaced-immobilized nucleic acid probes for small size DNA or RNA targets, utilizing optical or electrochemical methods, has been the goal for the gene chip technology. This study focuses on new probe design for introducing hairpin structural features and locked nucleic acid modification. We use three kinds of probes (DNA-LN, DNA-HP and LNA-HP) to prepare recognition layers via self-assembly processes on a gold substrate, and utilize AFM-based nanolithography technique to produce nanofeatures to observe the stiffness changes of oligonucleotide chains resulting from the formation of rigid double stranded duplexes when target sequence hybridizes to the probe. We also monitor the topographic changes upon exposure to the single mismatched and non-complementary targets as a function of time. The results reveal LNA-HP probes exhibit the highest response to discriminating single-point mutation in the base sequence. In addition, we study the effects of salt concentration, reaction temperature and the small size on the hybridization efficiency.

Dissertation (Ph.D.)--Auburn University,2006. / Abstract. Vita. Includes bibliographic references (p.110-113).

Recently, there has been increasing interest within the potential user community of Global Positioning System (GPS) for high precision navigation problems such as aircraft non precision approach, river and harbor navigation, real-time or kinematic surveying. In view of more and more GPS applications, the reliability of GPS is at this issue. The Global Positioning System (GPS) is a space-based radio navigation system that provides consistent positioning, navigation, and timing services to civilian users on a continuous worldwide basis. The GPS system receiver provides exact location and time information for an unlimited number of users in all weather, day and night, anywhere in the world. The work in this thesis will mainly focuss on how to model a Mathematical expression for tracking GPS Signal using Phase Locked Loop filter receiver. Mathematical formulation of the filter are of two types: the first order and the second order loops are tested successively in order to find out a compromised on which one best provide a zero steady state error that will likely minimize noise bandwidth to tracks frequency modulated signal and returns the phase comparator characteristic to the null point. Then the Z-transform is used to build a phase-locked loop in software for digitized data. Finally, a Numerical Methods approach is developed using either MATLAB or Mathematica containing the package for Gaussian elimination to provide the exact location or the tracking of a GPS in the space for a given a coarse/acquisition (C/A) code.

Linearity enhancement, especially within the front end of a wireless receiver IC design, is highly desirable since it allows the front-end to withstand strong interferers from co-existing communication standards or other wireless radiators. We propose an interferer suppression method based on feed-forward cancellation that uses an injectionlocked oscillator (ILO) to extract the interferer from the incident spectrum. The technique is expected to be useful in environments where a strong narrowband interferer appears along with a wideband desired signal, such as ultra-wideband (UWB) and emerging cognitive-radio applications. The ILO is further embedded within a phase-locked loop which provides several advantages including ILO center frequency self tuning and automatic phase alignment between the main signal path and the auxiliary path. An IC that uses this approach is implemented in a UMC 0.18[mu]m RFCMOS process. In measurement, the chip demonstrates 20dB suppression for phase and frequency modulated interferers while maintaining around 18dB power gain and noise figure below 5dB, measured with an off-chip balun for the desired signal. Techniques for canceling amplitude modulated interferers, though not included in the integrated circuit, were also demonstrated with an off chip amplitude control loop. Over 20dB rejection was obtained with AM interferers with properly scaled envelop signal applied to the ILO bias port. A second LNA was connected in cascade with the system to emulate the input stage of a down-conversion mixer and the cascaded P1dB was improved over 16dB with cancellation on. Gain compression above 13dB was also observed when auxiliary path was disabled, at the same input level as the P1dB with cancellation applied. / text

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

High-power, single-frequency, narrow-linewidth lasers emitting at tailored wavelength are desired for many applications, especially for precision spectroscopy. By way of a free-space resonator, optically pumped semiconductor lasers (OPSLs), a.k.a. vertical external-cavity surface-emitting lasers (VECSELs), can provide near diffraction-limited, high-quality Gaussian beams and are scalable in output power. Free space resonators also allow the insertion of the birefringent filter and the etalon to enforce single-frequency operation. In addition, the emission wavelengths of OPSLs are tailorable through bandgap engineering. These advantages above make OPSL a strong candidate of laser sources for spectroscopic applications including atomic spectroscopy as well as optical lattice clocks. In this research, a single-frequency laser source with high power is demonstrated by applying the injection-locking technique on OPSLs for the first time. The behaviors of the injection-locked OPSL are studied by varying parameters such as output coupling, injection wavelengths and injection power. It was found that the best injection wavelength is by approximately 2 nm shorter than the free-running slave laser at any given pump power. Below the lasing threshold for free-running operation, the laser starts the stimulated emission process as soon as it is pumped, working as a resonant amplifier. With proper parameters, the output power of the injection-locked laser exceeds the output power of its free-running condition. Over 9 W of single-frequency output power at 1015 nm is achieved. The output beam is near-diffraction-limited with Mₓ² = 1.04 and My² = 1.02. By analyzing the surface photoluminescence (PL) and the output performance of the laser, the saturation intensity of OPSLs is estimated to be 100 kW/cm² when the passive loss of 1.4% is assumed. The injection-locked system adds fairly low phase noise to that of the master laser. By measuring the beat note between the master laser and the injection-locked laser, the RMS values of the phase noise are 0.112 rad and 0.081 rad when using the T = 3% and T = 4% output couplers respectively.

The Phase Locked Loops (PLLs) are widely used in contemporary electronic systems for frequency synthesis, clock recovery, frequency multiplication and other purposes. Because of continuous increase in operating frequency of clocking systems the requirements on the clock spectral purity and low jitter became very demanding and are one of major designers' concerns.Frequency synthesizers used in microprocessors are integrated on the same substrate as the rest of the circuit and thus suffer from a substantial switching noise injected into global supply and ground busses. Usually when the reference signal comes from a crystal oscillator, VCO becomes a main source of phase noise. A designer of VCO needs to determine the best circuit structure by considering different prototypical perturbations scenarios and predicting the worst case and jitter response when the perturbation signals are switched on and off. Therefore the time efficient estimation of the jitter effects resulting from many shapes, frequencies and phases of perturbation is critical.The presented dissertation demonstrates simulation methodology for rapid estimation of jitter in oscillators, particularly in VCOs, caused by perturbation sources such as power supply and substrate couplings. The methodology is also extended to these types of PLLs in which the VCO instability is a main contributor to the output timing jitter.Simulation of oscillatory circuits is strongly effected by the round-off errors. Special technique was developed to eliminate these effects.The technique is applicable for predicting timing non-idealities for arbitrary perturbation shapes, frequencies and phases. Different jitter metrics can be easily extracted for all important perturbation scenarios.The methodology utilizes the new concept of the transient multi-cycle Voltage Impulse Sensitivity Function (VISF), which has been developed in the dissertation. It contains information about sensitivity of oscillator to noise injection and also allows for efficient prediction of the transient effects caused by switching on and off the perturbation sources. The methodology offers efficiency and great simplicity of use, which frees designers from complicated, time consuming analysis of data generated by a simulator. The very involved postprocessing of simulation data can be fully automated.

Single-frequency and mode-locked silver film ion-exchanged glass waveguide lasers as well as all-optical clock recovery based on birefringent fiber resonators have been experimentally and theoretically studied. The theory, modeling and fabrication process of silver film ion-exchange techniques, have been discussed and presented.The UV-written gratings on both IOG-1 active and passive glass have been studied. For the first time, with a high quality narrowband grating UV-printed on the passive section of a hybrid glass, a DBR waveguide single-frequency laser is demonstrated with the linewidth less than 1 MHz and the output power of 9 mW.Novel saturable absorbers based on a fiber taper embedded in carbon nanotubes (CNTs)/polymer composite were demonstrated. The saturable absorbers were utilized to build mode-locked fiber lasers, which were studied experimentally. A mode-locked ring laser utilizing an Er-Yb-codoped glass waveguide as the gain medium was also demonstrated. In addition, short cavity mode-locked waveguide lasers with CNTs film on the top were theoretically investigated, which shows a short cavity mode-locked waveguide laser is very promising.A new concept to perform multi-channel multi-rate all-optical clock recovery based on birefringent fiber-optic waveguide resonators was discussed. The concept has been advanced to polarization-insensitive operation. The experimental results, obtained as a proof-of-concept, agree well with numerical simulations.

This thesis presents an investigation into the power transmission limitations imposed on a VSC-HVdc converter by ac system strength and ac system impedance characteristics, quantified by the short circuit ratio (SCR). An important result of this study is that the operation of the converter is not only affected by the SCR’s magnitude, but is also significantly affected by the ac system’s impedance angle at the fundamental frequency. As the ac impedance becomes more resistive, the minimum SCR required at the rectifier side increases from that required for ideally inductive ac impedance, but it decreases at the inverter side. The finite megavolt ampere (MVA) limit of the VSC imposes a further limitation on power transfer, requiring an increase in the value of the minimum SCR. This limitation can be mitigated if additional reactive power support is provided at the point-common-connection. A state-space VSC model was developed and validated with a fully detailed non-linear EMT model. The model showed that gains of the phased-locked-loop (PLL), particularly at low SCRs greatly affect the operation of the VSC-HVdc converter and that operation at low SCRs below about 1.6 is difficult. The model also shows that the theoretically calculated power-voltage stability limit is not attainable in practice, but can be approached if the PLL gains are reduced. The thesis shows that as the VSC-HVdc converter is subject to large signal excitation, a good controller design cannot rely on small signal analysis alone. The thesis therefore proposes the application of optimization tools to coordinate the controls of multiple converters in a dc grid. A new method, the "single converter relaxation method", is proposed and validated. The design procedure of control gains selection using the single converter relaxation method for a multi-converter system is developed. A new method for selecting robust control gains to permit operation over a range of operation conditions is presented. The coordination and interaction of control parameters of multi-terminal VSC are discussed. Using the SCR information at converter bus, the gain scheduling approach to optimal gains is possible. However, compared to robust control gains setting, this approach is more susceptible to system instability.

Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply.