The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.

In this report a phase locked loop (PLL) system for grid voltage phase tracking has been investigated. The grid voltage phase angle contains critical information for connecting a power plant, such as a wave energy converter, to the grid. A synchronous reference frame PLL system with PI-regulator gains calculated with the symmetrical optimum method has been designed and simulations in SIMULINK have been made. For ideal grid conditions the phase angle was tracked fast and accurate. For non-ideal conditions the phase angle was tracked but with less accuracy, due to slow dynamics of the system, but still within acceptable margins. In order to test this system further it has to be implemented in a control system and tested when connected to the grid.

POTS (Plain Old Telephony Service) systems have traditionally been connected via synchronous connections. When installing new nodes in the telephone network, they may sometimes be connected via packet networks such as Ethernet. Ethernet is an asynchronous network which means that nodes connected to the network don’t have access to the same clock frequency if it is not provided in some other way. If two nodes have different clock frequency, the receiver’s buffer will eventually overflow or starve. While not being a severe problem for telephony, devices used for data transmission, e.g. modems and fax will not be able to function properly. To avoid this it is necessary to synchronize the nodes. This thesis investigates methods to synchronize nodes connected over Ethernet by simulating them in Matlab. The simulations show that under certain circumstances it is possible to produce a clock signal conforming to relevant standards.

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>µ</i> m CMOS process technology.

We comprehensively investigated the concentration effect of dispersed single-walled carbon nanotubes (SWCNTs) in polymer films for being a saturable absorber (SA) to stabilize the mode locking performance of the Erbium-doped fiber laser (EDFL) pulse through the diagnosis of its nonlinear properties of SA. The measured modulation depth was 1 to 4.5% as the thickness increased from 18 to 265 £gm. We obtained the stable pulse of the mode-locked EDFL (MLEDFL) when the full-width half-maximum (FWHM) decreased from 3.43 to 2.02 ps as the concentrations of SWCNTs SA increased from 0.125 to 0.5 wt%. At constant concentration of 0.125 wt%, the similar pulse shortening effect of the MLEDFL was also observed when the FWHM decreased from 3.43 to 1.85 ps was the thickness of SWCNTs SA increased from 8 to 100 £gm. In EDFL system, we vary group-velocity dispersion (GVD) with different cavity length to achieve optical pulse compression. We got the shortest pulsewidth was 713 fs, and the time-bandwidth product (TBP) was 0.345. An in-depth study on the stable mode-locked pulse formation employing SWCNTs SA, it is possible to fabricate the SWCNT films for use in high performance MLEDFL and utilization of many other low-cost nanodevices.

The dependence of thickness and concentration product (TCP) of single-wall carbon nanotubes saturable absorber (SWCNTs SA) on stabilizing and shortening pulse width in passively mode-locked erbium-doped fiber ring laser (MLEDFL) was investigated and measured. The TCP represented the amounts of SWCNTs, which the optical beam encountered when passing through the SWCNTs SA. If the TCP was smaller than 8.25 (£gm x wt%), the spectral bandwidth was below 2 nm. The pulse shaping was dominated by its own self amplitude modulation (SAM) of SWCNTs SA. With further increasing TCP, the soliton-like ML operation was achieved and the spectral bandwidth was expanded to 6 nm. For soliton-like mode locking (ML) operation, the area theorem dominated the pulse shaping. Through area theorem analysis, the estimation of SPM increased as the TCP increased. The adequate enhanced SPM for balancing the slight negative GVD was provided to generate soliton-like ML pulses shorten the pulse width. However, as the TCP increased, the soliton pulse energy decreased. The decreasing soliton pulse energy restricted the further pulse shortening. The results showed that the dependence of the pulse energy and nonlinear self phase modulation (SPM) on TCP enabled to determine the shortest pulse width in MLEDFL based on the area theorem. At optimized TCP of 70.93 (£gm x wt%), it was found that the shortest pulse width of 418 fs. In addition, based on the estimated SPM from area theorem, the nonlinear refractive index n2 was calculated at the level of 0.4 - 1 x 10^-15 m^2/W that was close to the literature values of 10^-15 - 10^-16 m2/W. It provides another way to estimate the nonlinear refractive index except for the Z-scan measurement. We could also estimate the SPM if an active Z-scan measurement was taken to obtain the nonlinear refractive index of the sample. We realized the trend of pulse energy through few samples in MLEDFL, the behavior of pulse width could be theoretically simulated based on area theorem. Hence, with the area theorem analysis, the optimized TCP of SWCNTs SA could be simulated and estimated to generate the shortest pulse width from the trends of pulse energy and estimated SPM. The significant effect of TCP on pulse energy, SPM, pulse width, and spectral bandwidth of MLFLs suggests that the TCP represents the total amount of SWCNTs in SA, which can be used as one of key parameters for characterizing the passive MLFL pulse width. Through the study of the dependence of TCP on ML pulses in MLEDFL, it may provide a guideline to fabricate an effective SWCNTs SA to generate the shortest pulse width of the MLEDFL.

In the current transmission systems, the transmission capacity is still not enough. The information bandwidth of the optical fiber communication system is limited by the optical amplifier bandwidth, and more efficient use of the bandwidth is a very important issue. Therefore, the amplitude and phase shift keying (APSK) is one attractive method of multi-bit per symbol modulation scheme to improve the spectral efficiency, and it can effectively increase the transmission capacity. To improve the capacity and the spectral efficiency, the advanced modulation format is effective, and the coherent detection scheme is also effective. However, an optical phase-locked loop (PLL) to lock the local oscillator (LO) phase and the signal phase required for the homodyne detection is still difficult to realize and it makes the receiver circuit complicated. Using the digital coherent receiver, the optical carrier phase information can be recovered by means of the digital signal processing (DSP), and this scheme enables to eliminate the optical PLL circuit by the phase estimation algorithm through the DSP. The stored data can be offline processed by using the MATLAB program. This master thesis is focusing on studying the transmission performance of the APSK format using the DSP in the digital coherent receiver. 497km transmission experiment has been conducted. Subsequently, the stored data are offline processed by the algorithms of the DSP. Then, the APSK performances between back-to-back and 497km transmission are compared.

The grid voltage is normally required to avoid transient current of the inverter due to asynchronously grid-paralleling connection. This paper presents a seamless transition method to allow the inverter to connect to the grid at any time with no requirement of the grid voltage. The control of the inverter consists of the droop control and the riding-through control. In the droop-controlled mode, the inverter can connect to the utility and supply power according to its rated capacity. On the other hand, the riding-through mode is proposed to suppress the transient current due to asynchronous paralleling. In this mode, the zero-current control is realized to reduce transient current and a phase-locked loop is designed to correct the angle of the inverter output voltage. In addition, the virtual inductance is implemented to improve transient current resulting from the mode transition back to the droop control mode. Design considerations of the seamless transition method are provided and test results are conducted to verify its effectiveness.

Coherent nonlinear effects such as Electromagnetically Induced Transparency (EIT), Coherent Population Trapping (CPT), and Slow light are studied in thermal Rb vapor by both continuous and pulsed laser fields. This work primarily includes three parts: (I) mode-locked rubidium laser and its applications (II) enhanced coupling between optical and sound waves in the forward direction via ultra-slow light (III) optical steering via ultra-slow light in rubidium vapor. In part(I), I describe the construction and study of a mode-locked rubidium laser operating at the Rb D1 line using an active mode-locking technique inside the laser cavity. The mode-locked laser field is used to observe coherent effects in a dense rubidium gas. In part(II), I experimentally demonstrate enhanced acoustic-optic coupling that occurs when the velocity of sound is close to the group velocity of light. Dragging of the light by effective motion of the gas in a Rb cell is the origin of enhanced coupling. Good agreement between theory and experiment is found. In part(III), I experimentally demonstrate optical beam deflection in coherently driven rubidium vapor due to the steep refraction index profile in the region of EIT.

Circuit optimization is extremely important in order to design today's high performance integrated circuits. As systems become more and more complex, traditional optimization techniques are no longer viable due to the complex and simulation intensive nature of the optimization problem. Two examples of such problems include clock mesh skew reduction and optimization of large analog systems, for example Phase locked loops. Mesh-based clock distribution has been employed in many high-performance microprocessor designs due to its favorable properties such as low clock skew and robustness. However, such clock distributions can become quite complex and may consist of hundreds of nonlinear drivers strongly coupled via a large passive network. While the simulation of clock meshes is already very time consuming, tuning such networks under tight performance constraints is an even daunting task. Same is the case with the phase locked loop. Being composed of multiple individual analog blocks, it is an extremely challenging task to optimize the entire system considering all block level trade-offs. In this work, we address these two challenging optimization problems i.e.; clock mesh skew optimization and PLL locking time reduction. The expensive objective function evaluations and difficulty in getting explicit sensitivity information make these problems intractable to standard optimization methods. We propose to explore the recently developed asynchronous parallel pattern search (APPS) method for efficient driver size tuning. While being a search-based method, APPS not only provides the desirable derivative-free optimization capability, but also is amenable to parallelization and possesses appealing theoretically rigorous convergence properties. In this work it is shown how such a method can lead to powerful parallel optimization of these complex problems with significant runtime and quality advantages over the traditional sequential quadratic programming (SQP) method. It is also shown how design-specific properties and speeding-up techniques can be exploited to make the optimization even more efficient while maintaining the convergence of APPS in a practical sense. In addition, the optimization technique is further enhanced by introducing the feature to handle non-linear constraints through the use of penalty functions. The enhanced method is used for optimizing phase locked loops at the system level.