The master thesis deals with the issue of long-term ECG recording, used in medicine for monitoring of cardiac anomalies. Author focuses on explaning the general concepts in the first part. Author describes measuring methods and issues associated with measuring. Comparison of existing devices and design of solution with own features are in next chapter. Next is comparison and selecting of formats for recording measured data and description of device connectivity. In next chapter author focuses on hardware design and implementation of device. After that author describes software solution design for microcontroller, Bluetooth module and smartphone. Author introduces possible improvements for future generation of the device and then describes results of testing at the end of this work.

<p>Deep ‘Analog Artificial Neural Networks’ (AANNs) perform complex classification problems with high accuracy. However, they rely on humongous amount of power to perform the calculations, veiling the accuracy benefits. The biological brain on the other hand is significantly more powerful than such networks and consumes orders of magnitude less power, indicating some conceptual mismatch. Given that the biological neurons are locally connected, communicate using energy efficient trains of spikes, and the behavior is non-deterministic, incorporating these effects in Artificial Neural Networks (ANNs) may drive us few steps towards a more realistic neural networks. </p> <p> </p> <p>Emerging devices can offer a plethora of benefits including power efficiency, faster operation, low area in a vast array of applications. For example, memristors and Magnetic Tunnel Junctions (MTJs) are suitable for high density, non-volatile Random Access Memories when compared with CMOS implementations. In this work, we analyze the possibility of harnessing the characteristics of such emerging devices, to achieve neuro-inspired solutions to intricate problems.</p> <p> </p> <p>We propose how the inherent stochasticity of nano-scale resistive devices can be utilized to realize the functionality of spiking neurons and synapses that can be incorporated in deep stochastic Spiking Neural Networks (SNN) for image classification problems. While ANNs mainly dwell in the aforementioned classification problem solving domain, they can be adapted for a variety of other applications. One such neuro-inspired solution is the Cellular Neural Network (CNN) based Boolean satisfiability solver. Boolean satisfiability (k-SAT) is an NP-complete (k≥3) problem that constitute one of the hardest classes of constraint satisfaction problems. We provide a proof of concept hardware based analog k-SAT solver that is built using MTJs. The inherent physics of MTJs, enhanced by device level modifications, is harnessed here to emulate the intricate dynamics of an analog, CNN based, satisfiability (SAT) solver. </p> <p> </p> <p>Furthermore, in the effort of reaching human level performance in terms of accuracy, increasing the complexity and size of ANNs is crucial. Efficient algorithms for evaluating neural network performance is of significant importance to improve the scalability of networks, in addition to designing hardware accelerators. We propose a scalable approach for evaluating Liquid State Machines: a bio-inspired computing model where the inputs are sparsely connected to a randomly interlinked reservoir (or liquid). It has been shown that biological neurons are more likely to be connected to other neurons in the close proximity, and tend to be disconnected as the neurons are spatially far apart. Inspired by this, we propose a group of locally connected neuron reservoirs, or an ensemble of liquids approach, for LSMs. We analyze how the segmentation of a single large liquid to create an ensemble of multiple smaller liquids affects the latency and accuracy of an LSM. In our analysis, we quantify the ability of the proposed ensemble approach to provide an improved representation of the input using the Separation Property (SP) and Approximation Property (AP). Our results illustrate that the ensemble approach enhances class discrimination (quantified as the ratio between the SP and AP), leading to improved accuracy in speech and image recognition tasks, when compared to a single large liquid. Furthermore, we obtain performance benefits in terms of improved inference time and reduced memory requirements, due to lower number of connections and the freedom to parallelize the liquid evaluation process.</p>

Dans les années à venir, l’industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine ‘‘Beyond CMOS’’, ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. Ainsi, le caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d’envisager la réalisation de transistors et de cellules mémoires à haute densité d’intégration, basse consommation. L’objectif principal de ce travail de thèse est d’explorer et d’évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DGSETs dans une approche ‘‘cellules standards’’ ; et iii) l’exploration d’architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l’aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en terme de consommation d’énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiques. / In this work, we have presented a physics-based analytical SET model for hybrid SET-CMOS circuit simulations. A realistic SET modeling approach has been used to provide a compact SET model that takes several conduction mechanisms into account and closely matches experimental SET characteristics. The model is implemented in Verilog-A language, and can provide suitable environment to simulate hybrid SET-CMOS architectures. We have presented logic circuit design technique based on double gate metallic SET at room temperature. We have also shown the flexibility that the second gate can bring in order to configure the SET into P-type and N-type. Given that the same device is utilized, the circuit design approach exhibits regularity of the logic gate that simplifies the design process and leads to reduce the increasing process variations. Afterwards, we have addressed a new Boolean logic family based on DG-SET. An evaluation of the performance metrics have been carried out to quantify SET technology at the circuit level and compared to advanced CMOS technology nodes. SET-based static memory was achieved and performances metrics have been discussed. At the architectural level, we have investigated both full DG-SET based arithmetic logic blocks (FA and ALU) and programmable logic circuits to emphasize the low power aspect of the technology. The extra power reduction of SETs based logic gates compared to the CMOS makes this technology much attractive for ultra-low power embedded applications. In this way, architectures based on SETs may offer a new computational paradigm with low power consumption and low voltage operation. We have also addressed a flexible logic design methodology based on DG-SET transmission gates. Unlike conventional design approach, the XOR / XNOR behavior can be efficiently implemented with only 4 transistors. Moreover, this approach allows obtaining reconfigurable XOR / XNOR gates by swapping the cell biasing. Given that the same device is utilized, the structure can be physically implemented and established in a regular manner. Finally, complex logic gates based on DG-SET transmission gates offer an improvement in terms of transistor device count and power consumption compared to standard complementary SETs implementations.Process variations are introduced through our model enabling then a statistical study to better estimate the SET-based circuit performances and robustness. SET features low power but limited operating frequency, i.e. the parasitics linked to the interconnects reduce the circuit operating frequency as the SET Ion current is limited to the nA range. In term of perspectives: i) detailed studying the impact on SET-based logic cells of process variation and random back ground charge ii) considering multi-level computational model and their associate architectures iii) investigating new computation paradigms (neuro-inspired architectures, quantum cellular automata) should be considered for future works.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

Les systèmes embarqués mobiles font partis intégrante de notre quotidien. Afin de les rendre plus adaptésaux usages, ils ont été miniaturisés et leur autonomie a été augmentée, parfois de façon très considérable.Toutefois, les propositions d’amélioration butent désormais sur les possibilités de la technologie des circuitsintégrés. Pour aller plus loin, il faut donc envisager de repenser la chaîne de traitement du signal afin deréduire la consommation de ces dispositifs. Cette thèse développe une approche originale pour exploiterefficacement l’échantillonnage par traversée de niveaux d’une part et, d’autre part, associe cet échantillonnageà une logique évènementielle afin de réduire drastiquement la consommation d’énergie des systèmesintégrés autonomes. Une méthode de discrétisation adaptée à une application de reconnaissance de signauxphysiologiques, utilisée comme exemple dans cette thèse, y est présentée. Un premier prototype en logiqueévènementielle (asynchrone) sur circuit FPGA a permis de valider cette stratégie et de démontrer les bénéficesde cet échantillonnage dédié en termes de réduction de l’activité par rapport à un échantillonnage uniforme.Un second prototype en logique asynchrone et conçu en technologie CMOS AMS 0.35 μm a permis de validerpar simulation électrique un gain extrêmement important sur la consommation électrique du dispositif. / Our everyday life is highly dependent on mobile embedded systems. In order to make them suitable to differentapplications, they have underwent size reduction and lifetime extension. However, these improvementsare currently limited by the possibilities of the integrated circuits technologies. In order to push back theboundaries, it is necessary to reconsider the whole digital signal processing chain from scratch to sustain thepower consumption reduction in this kind of system. This work develops on the first hand a strategy thatsmartly uses the level-crossing sampling scheme and on the other combines this sampling method with eventlogicto highly reduce the power consumption in mobile embedded systems. A discretisation method adaptedto the recognition of physiological patterns application is described. A first event-logic (asynchronous) prototypeimplemented on FPGA proved the potential benefits that an adapted sampling scheme could offersto reduce activity compared to a uniform sampling scheme. Electrical simulations performed on a secondprototype, also designed in asynchronous logic, with CMOS AMS 0.35 μm technology, validated a high gainin power consumption.

Given the current state of input/output (I/O) and storage devices in petascale systems, incremental solutions would be ineffective when implemented in exascale environments. According to the "The International Exascale Software Roadmap", by Dongarra, et al. existing I/O architectures are not sufficiently scalable, especially because current shared file systems have limitations when used in large-scale environments. These limitations are: Bandwidth does not scale economically to large-scale systems, I/O traffic on the high speed network can impact on and be influenced by other unrelated jobs, and I/O traffic on the storage server can impact on and be influenced by other unrelated jobs. Future applications on exascale computers will require I/O bandwidth proportional to their computational capabilities. To avoid these limitations C. Filippidis, C. Markou, and Y. Cotronis proposed the IKAROS framework. In this thesis project, the capabilities of the publicly available elastic-transfer (eT) module which was directly derived from the IKAROS, will be expanded. The eT uses Google’s Gmail service as an utility for efficient meta-data management. Gmail is based on the IMAP protocol, and the existing version of the eT framework implements the Internet Message Access Protocol (IMAP) client-server connection through the ‘‘Inbox’’ module from the Node Package Manager (NPM) of the Node.js programming language. This module was used as a proof of concept, but in a production environment this implementation undermines the system’s scalability and there is an inefficient allocation of the system’s resources when a large number of concurrent requests arrive at the eT′s meta-data server (MDS) at the same time. This thesis solves this problem by adopting an asynchronous non-blocking event driven approach to implement the IMAP client-server connection. This was done by integrating and modifying the ‘‘Imap’’ NPM module from the NPM repository to suit the eT framework. Additionally, since the JavaScript Object Notation (JSON) format has become one of the most widespread data-interchange formats, eT′s meta-data scheme is appropriately modified to make the system’s meta-data easily parsed as JSON objects. This feature creates a framework with wider compatibility and interoperability with external systems. The evaluation and operational behavior of the new module was tested through a set of data transfer experiments over a wide area network environment. These experiments were performed to ensure that the changes in the system’s architecture did not affected its performance. / Givet det nuvarande läget för input/output (I/O) och lagringsenheter för system i peta-skala, skulle inkrementella lösningar bli ineffektiva om de implementerades i exa-skalamiljöer. Enligt ”The International Exascale Software Roadmap”, av Dongarra et al., är nuvarande I/O-arkitekturer inte tillräckligt skalbara, särskilt eftersom nuvarande delade filsystem har begränsningar när de används i storskaliga miljöer. Dessa begränsningar är: Bandbredd skalar inte på ett ekonomiskt sätt i storskaliga system, I/O-trafik på höghastighetsnätverk kan ha påverkan på och blir påverkad av andra orelaterade jobb, och I/O-trafik på lagringsservern kan ha påverkan på och bli påverkad av andra orelaterade jobb. Framtida applikationer på exa-skaladatorer kommer kräva I/O-bandbredd proportionellt till deras beräkningskapacitet. För att undvika dessa begränsningar föreslog C. Filippidis, C. Markou och Y. Cotronis ramverket IKAROS. I detta examensarbete utökas funktionaliteten hos den publikt tillgängliga modulen elastic-transfer (eT) som framtagits utifrån IKAROS. Den befintliga versionen av eT-ramverket implementerar Internet Message Access Protocol (IMAP) klient-serverkommunikation genom modulen ”Inbox” från Node Package Manager (NPM) ur Node.js programmeringsspråk. Denna modul användes som ett koncepttest, men i en verklig miljö så underminerar denna implementation systemets skalbarhet när ett stort antal värdar ansluter till systemet. Varje klient begär individuellt information relaterad till systemets metadata från IMAP-servern, vilket leder till en ineffektiv allokering av systemets resurser när ett stort antal värdar är samtidigt anslutna till eT-ramverket. Denna uppsats löser problemet genom att använda ett asynkront, icke-blockerande och händelsedrivet tillvägagångssätt för att implementera en IMAP klient-serveranslutning. Detta görs genom att integrera och modifiera NPM:s ”Imap”-modul, tagen från NPM:s katalog, så att den passar eT-ramverket. Eftersom formatet JavaScript Object Notation (JSON) har blivit ett av de mest spridda formaten för datautbyte så modifieras även eT:s metadata-struktur för att göra systemets metadata enkelt att omvandla till JSON-objekt. Denna funktionalitet ger ett bredare kompatibilitet och interoperabilitet med externa system. Utvärdering och tester av den nya modulens operationella beteende utfördes genom en serie dataöverföringsexperiment i en wide area network-miljö. Dessa experiment genomfördes för att få bekräftat att förändringarna i systemets arkitektur inte påverkade dess prestanda.