The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today’s shared buses with packet-switched router networks. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as three-dimensional (3D) graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. This work demonstrates that a computational fabric built using optimized building blocks can provide high levels of performance in an energy efficient manner. The thesis details an integrated 80- Tile NoC architecture implemented in a 65-nm process technology. The prototype is designed to deliver over 1.0TFLOPS of performance while dissipating less than 100W. This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power. In a 150-nm sixmetal CMOS process, the 12.2 mm2 router contains 1.9-million transistors and operates at 1 GHz at 1.2 V supply. We next describe a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulation loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. A combination of algorithmic, logic and circuit techniques enable multiply-accumulate operations at speeds exceeding 3GHz, with singlecycle throughput. This approach reduces the latency of dependent FPMAC instructions and enables a sustained multiply-add result (2FLOPS) every cycle. The optimizations allow removal of the costly normalization step from the critical accumulation loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230-K transistors. Silicon achieves 6.2-GFLOPS of performance while dissipating 1.2 W at 3.1 GHz, 1.3 V supply. We finally present the industry's first single-chip programmable teraFLOPS processor. The NoC architecture contains 80 tiles arranged as an 8×10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined singleprecision FPMAC units which feature a single-cycle accumulation loop for high throughput. The five-port router combines 100 GB/s of raw bandwidth with low fall-through latency under 1ns. The on-chip 2D mesh network provides a bisection bandwidth of 2 Tera-bits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100-M transistors. The fully functional first silicon achieves over 1.0TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07-V supply. It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results demonstrate that the NoC architecture successfully delivers on its promise of greater integration, high performance, good scalability and high energy efficiency.

In this project a new type of metal oxide semiconductor (MOS) sensor for biosensing was investigated. With the use of a porous gold film as aninternal reference electrode, measurements of pH were performed in liquid. This new approach for liquid measurements demands new methods andstudies to increase the conductivity and adhesion in liquid of the porous gold film. The films have been deposited, either by sputtering orevaporation. Extensive studies included the investigation of depositions parameters on film structure and investigating the film morphology. Thesurface structure was studied with a scanning electron microscope (SEM). pH measurements were preformed with promising results. The adhesionof the electrode was greatly improved by using grains of titanium underneath the gold film. This new approach could lead to new applications anddevices for MOS sensors and its sensor relatives.

XMM-Newton is a X-ray telescope launched december 1999, by the European Space Agency, ESA. On board XMM-Newton are two EPIC-MOS X-ray detectors. The detectors are build by Charged Coupled Devices (CCDs), of Metal Oxide Semi-conductor type. The EPIC-MOS cameras have four science operating modes. This project aims to evaluate the calibration for one of these four modes, the timing mode. The evaluation is divided into two parts. The first part is the evaluation of the flux calibration, performed by analysing various observation made in timing mode. The second part is the evaluation of timing properties by performing timing analysis of XMM-Newton observations of the Crab nebula compared to observations made in the radio wavelengths.

This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link. The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity. The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

In this study, the characteristics of Nickel-doped LPD-TiO2 films on silicon substrate were investigated. In our experiment, we do some measurement about physical, chemical and electrical properties for undoped and Nickel-doped LPD-TiO2 films and discussed with them. The TiO2 film thickness was characterized by field emission scanning electron microscopy ( FE-SEM ), structure was characterized by X-ray diffraction (XRD), chemical properties was characterized by X-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FT-IR) and electrical properties was characterized by leakage current: current-voltage (B1500A) and dielectric constant: capacitance-voltage (4980A). For the electrical property improvements, we investigated the Ni-doped LPD-TiO2 films by the post-anneal treatments in nitrogen, oxygen and nitrous oxide ambient. For nickel doping, the nickel chloride was used as the doping solution and the electrical characteristics were improved. After thermal annealing in nitrous oxide at 700 oC, the dielectric constant of polycrystalline titanium oxide film is 29 and can be improved to 94 with nickel doping.

An uniform titanium oxide film was grown on indium tin oxide/glass substrate with the aqueous solutions of ammonium hexafluoro-titanate and boric acid. The as-deposition titanium oxide film shows good electrochromic property because of fluorine passivation on defects and dangling bonds. The transmittance of as-grown titanium oxide on indium tin oxide/glass with a thickness of 270 nm is about 85% at the wavelength of 550 nm. By 50 times electrochromic cycling test, the transparency ratio of TiO2 film is kept at 45% between fully colored state and fully bleached state at the wavelength of 550 nm. Under ultraviolet illumination, the growth of titanium oxide film grown is enhanced. The root mean squared value of surface roughness is improved from 3.723 to 0.523 nm. Higher fluorine concentration from (NH4)2TiF6 passivate defects and dangling bonds of titanium oxide during the growth. After 50 times electrochromic cycling test, the transparency ratio UV-TiO2 is improved from 37.5% to 42.4% at the wavelength of 550 nm. The electrical characteristics of nickel-doped titanium oxide films on p-type (100) silicon substrate by liquid phase deposition were investigated. For nickel doping, the nickel chloride was used as the doping solution and the electrical characteristics were improved. After thermal annealing in nitrous oxide at 700 oC, the dielectric constant of polycrystalline titanium oxide film is 29 and can be improved to 94 with nickel doping. Uniform nickel oxide film was grown on a conducting glass substrate with the aqueous solution of saturated NiF2¡E4H2O solution and H3BO3. The quality of NiO is improved after thermal annealing at 300 oC in air from the decrease of oxygen vacancy and better F ion passivation on defects and dangling bonds. The transmittance of as-deposited NiO/ITO/glass with a thickness of 100 nm is about 78% and improved to 88% after annealing at the wavelength of 550 nm. By the electrochromic cycling test 50 times on annealed NiO film, the transparency ratio is kept at 48% between fully colored state and fully bleached state at the wavelength of 550 nm. By the memory time test, the annealed LPD-NiO film has shorter memory time. The growth of nickel oxide film grown on indium-tin oxide/glass substrate by liquid phase deposition is enhanced under ultraviolet photo-irradiation was studied. a-Ni(OH)2 dominates the composition of as-grown NiO film. After thermal treatment at 300 oC,a-Ni(OH)2 is transformed into NiO. For thermally treated NiO under ultraviolet photo-irradiation, the recrystallization and the colored and bleached transmittance after 50 times electrochromic test were improved. Both improvements come from fluorine passivation. Transparent and conductive thin films consisting of p-type nickel oxide (NiO) semiconductors were prepared by liquid phase deposition. A resistivity of 8 x 10-1 -cm was obtained for NiO films prepared at liquid phase deposition. The transmittance of NiO is almost 70 % in the 550 nm wavelength was obtained for a 384.3 nm thick NiO film.

<p>XMM-Newton is a X-ray telescope launched december 1999, by the European Space Agency, ESA. On board XMM-Newton are two EPIC-MOS X-ray detectors. The detectors are build by Charged Coupled Devices (CCDs), of Metal Oxide Semi-conductor type. The EPIC-MOS cameras have four science operating modes. This project aims to evaluate the calibration for one of these four modes, the timing mode.</p><p>The evaluation is divided into two parts. The first part is the evaluation of the flux calibration, performed by analysing various observation made in timing mode. The second part is the evaluation of timing properties by performing timing analysis of XMM-Newton observations of the Crab nebula compared to observations made in the radio wavelengths.</p>

Le travail exposé dans cette thèse cible les nouveaux matériaux susceptibles d'être intégrés dans les mémoires et les applications à base de transistors MOS. Il est divisé en trois chapitres principaux. Le premier chapitre traite des contraintes de fabrication des dispositifs. Nous abordons aussi l'état de l'art ainsi que les objectifs industriels à courte échéance. Ce premier chapitre est important pour donner au lecteur les bases technologiques pour comprendre pourquoi des investissements gigantesques sur ces matériaux sont consentis dans l'industrie microélectronique et la recherche associée. Le second chapitre traite des méthodes de dépôt et croissance des isolants étudiés dans cette thèse. De même nous décrivons au mieux les moyens de caractérisation pour analyser les propriétés physiques et électriques de ces diélectriques. Quelques exemples de matériaux analysés aideront le lecteur à comprendre facilement notre méthode d'investigation scientifique. Le dernier chapitre est une revue de mon travail publié dans des journaux scientifiques de renommée internationale ou d'exposés dans des conférences majeures. Ce chapitre 3 est sous-divisé en 3 sections. La première et deuxième traite de la compréhension des propriétés des silicates d'aluminium-lanthane et oxydes de terre rare obtenus par différentes méthodes de dépôt et recuit. Les résultats ajoutés aux résultats de l'art antérieur donnent un aperçu significatif de notre recherche d'un matériau candidat potentiel comme isolant high k. La dernière section est dédiée aux oxydes de titane et de silicates de titane.

Ce mémoire traite de la modélisation et de l'évaluation des performances d'un nouveau composant de puissance, le transistor MOS à tranchées. Plus précisément, on présente tout d'abord l'évolution des structures MOS de puissance basse tension depuis les années 70 jusqu'au transistor MOS à tranchées dont les principales propriétés sont énumérées. On réalise ensuite une étude des mécanismes - analyse statique à l'état passant et à l'état bloqué, analyse dynamique - intervenant dans les diverses zones du composant. Sur la base de cette étude, on établit un modèle de ce transistor pour le logiciel de simulation des circuits SPICE. Les procédures d'acquisition des paramètres de ce modèle sont précisées. Ce modèle ainsi obtenu est ensuite validé sur deux familles de divers composants MOS de puissance industriels. Enfin, les limites de performances statiques et dynamiques des transistors VDMOS et MOS à tranchées sont étudiées et comparées. Il est principalement montré que, dans le domaine des basses tensions, le transistor MOS à tranchées affiche des performances supérieures au transistor VDMOS en termes de résistance passante spécifique et de densité d'intégration. Les études analytiques et les simulations bidimensionnelles des deux types de composants montrent également que cette supériorité est appelée à s'accroître dans les années à venir.

Reproduction de : Thèse de doctorat : Conception des circuits microélectroniques et microsystèmes : Toulouse, INPT : 2007. / Titre provenant de l'écran-titre. Bibliogr. 139 réf.