This thesis deals with modeling, simulation and implementation of Load Commutated SCR based current source Inverter (LCI) fed squirrel cage induction motor drive with sinusoidal voltage and sinusoidal current. In the proposed system, the induction motor is fed by an LCI. A three level diode clamped voltage source inverter (VSI) is connected at the motor terminal with ac chokes connected in series with it. The VSI currents are controlled in such a manner that it injects the reactive current demanded by the induction motor and the LCI for successful commutation of the SCRs in the LCI. Additionally, it absorbs the harmonic frequency currents to ensure that the induction motor draws sinusoidal current. As a result, the nature of the motor terminal voltage is also sinusoidal. The concept of load commutation of the SCRs in the LCI feeding an induction motor load is explained with necessary waveforms and phasor diagrams. The necessity of reactive compensation by the active filter connected at the motor terminal for the load commutation of the thyristors, is elaborated with the help of analytical equations and phasor diagrams. The requirement of harmonic compensation by the same active filter to achieve sinusoidal motor current and motor voltage, is also described. Finally, to achieve the aforementioned induction motor drive, the VA ratings of the active filter (VSI) and the CSI with respect to VA rating of the motor, are determined theoretically. The proposed drive scheme is simulated under idealized condition. Simulation results show good steady state and dynamic response of the drive system. Load commutation of the SCRs in the LCI and the sinusoidal profile of motor current and voltage, have been demonstrated. As in LCI fed synchronous motor drives, a special mode of operation is required to run up the induction motor from standstill. As the SCRs of the LCI are load commutated, they need motor terminal voltages for commutation. At standstill these voltages are zero. So, a starting strategy has been proposed and adopted to start the motor with the aid of the current controlled VSI to accelerate until the motor terminal voltages are high enough for the commutation of the SCRs in the LCI. The proposed drive is implemented on an experimental setup in the laboratory. The IGBT based three level diode clamped VSI has been fabricated following the design of the standard module in the laboratory. A generalized digital control platform is also developed using a TMS320F2407A DSP. Two, three phase thyristor bridges with necessary firing pulse circuits have been used as the phase controlled rectifier and the LCI respectively. Appropriate protection scheme for such a drive is developed and adopted to operate the drive. Relevant experimental results are presented. They are observed to be in good agreement with the simulation results. The effect of capacitors connected at the output of the LCI in the commutation process of the SCRs in the LCI is studied and analyzed. From the analysis, it is understood that the capacitors form a parallel resonating pair with filter inductor and the motor leakage inductance, which results in an undesired oscillation in the terminal voltage during each of the commutation intervals leading to commutation failure. So, in the final system, the capacitors are removed to eliminate any chance of commutation failure of the SCRs in the LCI. It is shown by experiment that the commutation of the SCRs takes place reliably in the absence of the capacitors also. The commutation process is studied and analyzed without the capacitors to understand the motor terminal voltage waveform of the experimental results.

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.

Les travaux développés durant cette thèse concernent la détection et l'identification des défauts simples et multiples d'ouverture des transistors dans un convertisseur statique associé à une machine asynchrone. Pour aborder cette problématique, nous avons commencé par l'analyse des potentialités, des faiblesses et des incertitudes des techniques qui ont initiés notre démarche. Ensuite, nous avons présenté deux méthodologies permettant d'analyser les performances du moteur asynchrone en présence des défauts dans une ou plusieurs cellules de commutation. Cette étude préliminaire nous a permis ainsi de proposer deux nouvelles stratégies de diagnostic sans référence basées sur l'approche signal. Les signaux électriques (courants ou tensions) disponibles à la sortie du convertisseur statique sont utilisés pour alimenter le processus de diagnostic. La première stratégie retenue est basée sur l'analyse qualitative des tensions de sortie entre phases du convertisseur et des signaux de commande appliqués aux transistors pendant les instants de commutation. Grâce à une représentation instantanée de ces grandeurs, à l'échelle de la période de découpage, nous avons pu mettre en évidence des caractéristiques favorables à la détection des défauts simples et multiples d'ouverture des transistors. L'implémentation pratique de cette première approche a été réalisée au moyen d'une technologie analogique permettant ainsi de minimiser le temps de retard à la détection jusqu'à quelques dizaines de microsecondes. / The main goal of this thesis concerns the detection and identification of simple and multiple open-circuit faults in voltage source inverters (VSIs)-fed induction motor drives. In first step, the potentialities, the weaknesses as well as the uncertainties of the previously published works have been discussed. The second step was dedicated to the study of the inverter faults impact on the induction motor. For this purpose, we have proposed two methodologies permitting the characterization of the electromagnetic torque behaviour as well as the electric variables of the induction motor under the open- and short-circuit faults. These preliminary studies allowed to propose two novel signal-based approaches for open-circuit fault diagnosis in voltage source inverter. The measured outputs inverter voltages and currents have been used as the input quantities for the fault detection and identification (FDI) process. The first approach consists in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. For this purpose, we have adopted an instantaneous representation of these variables, which permits their analysis over one switching period. The fault diagnosis scheme is achieved using simple analog device. This circuit allows an accurate single and multiple faults diagnosis, and a minimization of the fault detection time which becomes about a few tens of microseconds.

Considerando-se o atual estagio de desenvolvimento das máquinas elétricas, tanto em termos de ferramentas computacionais auxiliares nas simulações e nos projetos, quanto de materiais e sistemas eletrônicos de acionamento e controle, propõe neste trabalho a construção de um dispositivo eletromecânico, na classe dos motores elétricos lineares, que atenda as necessidades e se aplique a bioengenharia, mais propriamente as próteses de membro superior, na forma de acionador translacional. Este dispositivo deve substituir os sistemas que utilizam motores elétricos rotativos com mecanismos de adaptação mecânica (roldanas, vários fios, redutores), que convertem o movimento rotacional em linear. Também, os dispositivos híbridos, como atuadores eletro-hidráulicos e eletropneumáticos, que necessitam de fontes de energia de naturezas diferentes da eletroeletrônica, podem ser substituídos pelas maquinas elétricas lineares. Uma revisão dos conceitos relacionados a área de bioengenharia e feita, destacando-se os mecanismos de transmissão existentes. E apresentada uma analise comparativa entre os principais motores lineares, enfatizando-se as características construtivas, as vantagens e as desvantagens de cada um, relacionados a aplicação. A escolha da maquina a ser projetada e construída recaiu no motor linear síncrono, com imas permanentes na superfície da parte móvel, em uma estrutura tubular. Para esta maquina, e exposta uma metodologia de projeto, baseando-se nos seguintes tópicos: equacionamento do circuito magnético, cálculos de parâmetros utilizando-se o método dos elementos finitos e modelagem matemática por meio das equações por fase. Apos a etapa teórica, a construção da maquina e apresentada juntamente com os ensaios experimentais, possibilitando a comparação das características reais em relação ao projeto inicial. Por fim, o motor e aplicado ao dedo artificial, verificando-se a sua capacidade de substituição do motor rotativo. / By means of the latest technological advances of the electrical machines, both in terms of computational aids in simulations and designs, materials and electronic systems of drive and control, this work put forward the construction of an electromechanical device, in the class of the linear motors. It will be applied to bioengineering area, in particular in upper limb prostheses, in the form of a translational actuator. This linear motor must substitute the systems that use electric rotational motors with planetary gears and lead screw transmission, to convert the rotational movement into linear. The hybrid mechanisms, like electro pneumatic/hydraulic actuators, which need energy sources different from electronics, can be changed for the linear electric machines too. A review about bioengineering topics is done, where the existent mechanical mechanisms are highlighted. According to the application necessities, the advantages and disadvantages of different topologies of electric linear machines are compared and the constructive characteristics are emphasized. The tubular linear synchronous motor, with permanent magnets on the surface of the mobile part, was chosen to be applied to hand prostheses. To this machine, a design methodology is presented for calculating the motor dimensions, based on the following subjects: magnetic circuit equating, finite element analyses to evaluate parameters and machine dynamic modeling. After the theorethical stage, the construction of the machine is presented with the experimental results, allowing comparisons between the real characteristics and the initial design features of the motor. Finally, the machine is applied to an artificial finger to verify its capability to replace the rotational motor.

Considerando-se o atual estagio de desenvolvimento das máquinas elétricas, tanto em termos de ferramentas computacionais auxiliares nas simulações e nos projetos, quanto de materiais e sistemas eletrônicos de acionamento e controle, propõe neste trabalho a construção de um dispositivo eletromecânico, na classe dos motores elétricos lineares, que atenda as necessidades e se aplique a bioengenharia, mais propriamente as próteses de membro superior, na forma de acionador translacional. Este dispositivo deve substituir os sistemas que utilizam motores elétricos rotativos com mecanismos de adaptação mecânica (roldanas, vários fios, redutores), que convertem o movimento rotacional em linear. Também, os dispositivos híbridos, como atuadores eletro-hidráulicos e eletropneumáticos, que necessitam de fontes de energia de naturezas diferentes da eletroeletrônica, podem ser substituídos pelas maquinas elétricas lineares. Uma revisão dos conceitos relacionados a área de bioengenharia e feita, destacando-se os mecanismos de transmissão existentes. E apresentada uma analise comparativa entre os principais motores lineares, enfatizando-se as características construtivas, as vantagens e as desvantagens de cada um, relacionados a aplicação. A escolha da maquina a ser projetada e construída recaiu no motor linear síncrono, com imas permanentes na superfície da parte móvel, em uma estrutura tubular. Para esta maquina, e exposta uma metodologia de projeto, baseando-se nos seguintes tópicos: equacionamento do circuito magnético, cálculos de parâmetros utilizando-se o método dos elementos finitos e modelagem matemática por meio das equações por fase. Apos a etapa teórica, a construção da maquina e apresentada juntamente com os ensaios experimentais, possibilitando a comparação das características reais em relação ao projeto inicial. Por fim, o motor e aplicado ao dedo artificial, verificando-se a sua capacidade de substituição do motor rotativo. / By means of the latest technological advances of the electrical machines, both in terms of computational aids in simulations and designs, materials and electronic systems of drive and control, this work put forward the construction of an electromechanical device, in the class of the linear motors. It will be applied to bioengineering area, in particular in upper limb prostheses, in the form of a translational actuator. This linear motor must substitute the systems that use electric rotational motors with planetary gears and lead screw transmission, to convert the rotational movement into linear. The hybrid mechanisms, like electro pneumatic/hydraulic actuators, which need energy sources different from electronics, can be changed for the linear electric machines too. A review about bioengineering topics is done, where the existent mechanical mechanisms are highlighted. According to the application necessities, the advantages and disadvantages of different topologies of electric linear machines are compared and the constructive characteristics are emphasized. The tubular linear synchronous motor, with permanent magnets on the surface of the mobile part, was chosen to be applied to hand prostheses. To this machine, a design methodology is presented for calculating the motor dimensions, based on the following subjects: magnetic circuit equating, finite element analyses to evaluate parameters and machine dynamic modeling. After the theorethical stage, the construction of the machine is presented with the experimental results, allowing comparisons between the real characteristics and the initial design features of the motor. Finally, the machine is applied to an artificial finger to verify its capability to replace the rotational motor.

The use of insulated-gate bipolar transistor (IGBT)-based power converters is increasing exponentially. This is due to high performance of these devices in terms of efficiency and switching speed. However, due to the switching action, high frequency electromagnetic interference (EMI) noises are generated. Design of a power converter with reduced EMI noise level is one of the primary objectives of this research. The first part of the work focuses on designing common-mode (CM) filters, which can be integrated with differential-mode (DM) filters for three-phase pulse-width modulation (PWM) rectifier-based motor drives. This work explores the filter design based on the CM equivalent circuit of the drive system. Guidelines are provided for selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed topology. Analytical results based on Bode plot of the transfer functions are presented, which suggest effective EMI reduction. Experimental results based on EMI measurement on the grid side and CM current measurement on the motor side are presented. These results validate the effectiveness of the filter. In the second part of the work, it is shown that inclusion of CM filters into DM filters results in resonance oscillations in the CM circuit. An active damping strategy is proposed to damp the oscillations in both line-to-line and line-to-ground ac voltages and currents. An approach based on pole placement by state feedback is used to actively damp both the DM and CM filter oscillations. Analytical expressions for state-feedback controller gains are derived for both continuous-and discrete-time models of the filter. Trade-off in selection of the active damping gain on the lower-order grid current harmonics is analysed using a weighted admittance function method. In the third part of the work, single-phase grid-connected power converters are considered. An integrated CM filter with DM LCL filter is proposed. The work explores the suitability of PWM methods for single-phase and parallel single-phase grid-connected power converters. It is found that bipolar PWM and unipolar PWM with 180◦interleaving angle are suitable for single-phase and parallel single-phase power converters, respectively. The proposed configuration along with the PWM methods reduces the CM voltage, CM current, and EMI noise level effectively. It is also shown that the suggested circuit is insensitive to nonidealities of the power converter such as dead-time mismatch, mismatch in converter-side inductors, unequal turn on and turn off of the switches, and propagation delays. In the fourth part of the work, the inter-phase inductor in parallel interleaved power converters is integrated with LCL filter boost inductor. Different variant designs are presented and compared with the proposed structure. It is shown that the proposed structure makes use of standard core geometries and consumes lesser core material as well as copper wire. Hence, it reduces the overall size and cost of the power converter. In the present work, a 10kVA three-phase back-to-back connected with input LCL filter and output dv/dt filter, a 5kVA single-phase grid-connected power converter with LCL filter, and a 7.5kVA parallel single-phase grid-connected power converter with LCL filter are fabricated in the laboratory to evaluate and validate the proposed methods. The experimental results validate the proposed methods that result in significant EMI performance improvement of grid-connected power converters.

Voltage source inverter (VSI) fed induction motors are increasingly used in industrial and transportation applications as variable speed drives. However, VSIs generate non-sinusoidal voltages and hence result in harmonic distortion in motor current, motor heating, torque pulsations and increased acoustic noise. Most of these undesirable effects can be reduced by increasing the switching frequency of the inverter. This is not necessarily true for acoustic noise. Acoustic noise does not decrease monotonically with increase in switching frequency since the noise emitted depends on the proximity of harmonic frequencies to the motor resonant frequencies. Also there are practical limitations on the inverter switching frequency on account of device rating and losses. The switching frequency of many inverters often falls in the range 2 kHz - 6 kHz where the human ear is highly sensitive. Hence, the acoustic noise emission from the motor drive is of utmost important. Further, the acoustic noise emitted by the motor drive is known to depend on the waveform quality of the voltage applied. Hence, the acoustic performance varies with the pulse width modulation (PWM) technique used to modulate the inverter, even at the same modulation index. Therefore a comprehensive study on the acoustic noise aspects of induction motor drive is required. The acoustic noise study of the motor drive poses multifaceted challenges. A simple motor model is sufficient for calculation of total harmonic distortion (THD). A more detailed model is required for torque pulsation studies. But the motor acoustic noise is affected by many other factors such as stator winding distribution, space harmonics, geometry of stator and rotor slots, motor irregularities, structural issues controlling the resonant frequency and environmental factors. Hence an accurate model for acoustic noise would have to be very detailed and would span different domains such as electromagnetic fields, structural engineering, vibration and acoustics. Motor designers employ such detailed models along with details of the materials used and geometry to predict the acoustic noise that would be emitted by a motor and also to design a low-noise motor. However such detailed motor model for acoustic noise purposes and the necessary material and constructional details of the motor are usually not available to the user. Also, certain factors influencing the acoustic noise change due to wear and tear during the operational life of the motor. Hence this thesis takes up an experimental approach to study the acoustic noise performance of an inverter-fed induction motor at any stage of its operating life. A 10 kVA insulated gate bipolar transistor (IGBT) based inverter is built to feed the induction motor; a 6 kW and 2.3 kW induction motors are used as experimental motors. A low-cost acoustic noise measurement system is also developed as per relevant standards for measurement and spectral analysis of the acoustic noise emitted. For each PWM scheme, the current and acoustic noise measurements are carried out extensively at different carrier frequencies over a range of fundamental frequencies. The main cause of acoustic noise of electromagnetic origin is the stator core vibration, which is caused by the interaction of air-gap fluxes produced by fundamental current and harmonic currents. In this thesis, an experimental procedure is suggested for the acoustic noise characterization of an induction motor inclusive of determination of resonant frequencies. Further, based on current and acoustic noise measurements, a vibration model is proposed for the stator structure. This model is used to predict the acoustic noise pertaining to time harmonic currents with reasonable accuracy. Literature on motor acoustic noise mainly focuses on sinusoidal PWM (SPWM), conventional space vector PWM (CSVPWM) and random PWM (RPWM). In this thesis, acoustic noise pertaining to two bus-clamping PWM (BCPWM) schemes and an advanced bus-clamping PWM (ABCPWM) scheme is investigated. BCPWM schemes are mainly used to reduce the switching loss of the inverter by clamping any of the three phases to DC rail for 120◦ duration of the fundamental cycle. Experimental results show that these BCPWM schemes reduce the amplitude of the tonal component of noise at the carrier frequency, compared to CSVPWM. Experimental results with ABCPWM show that the overall acoustic noise produced by the motor drive is reduced at low and medium speeds if the switching frequency is above 3 kHz. Certain spread in the frequency spectrum of noise is also seen with both BCPWM and ABCPWM. To spread the acoustic noise spectrum further, many variable-frequency PWM schemes have been suggested by researchers. But these schemes, by and large, increase the current total harmonic distortion (THD) compared to CSVPWM. Thus, a novel variable-frequency PWM (VFPWM) method is proposed, which offers reduced current THD in addition to uniformly spread noise spectrum. Experimental results also show spread in the acoustic noise spectrum and reduction in the dominant noise components with the proposed VFPWM. Also, the current THD is reduced at high speeds of the motor drive with the proposed method.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

No description available.