Contrôleurs utilisés dans les systèmes autotestables pour le test des sorties combinatoires ou séquentielles. Conception des contrôleurs NMOS à partir de l'assemblage des cellules, des règles de conception pour celle-ci, et des hypothèses de pannes pouvant survenir. Les considérations pratiques sont basées sur des hypothèses de pannes analytiques

This thesis presents the modeling and fabrication of a new solid-state device meant to be used for digital logic circuits. Most current logic circuits are based on MOSFETs. The new logic device uses some of the same operating principles, but also relies on optical illumination to provide input power. In order to obtain the desired current-voltage behavior of the new device, the Silvaco (Atlas) device simulation was used to give some insight into the correct doping levels in the semiconductor and device geometries. Prototypes were fabricated on p-type silicon wafers using CMOS fabrication processes including oxide growth, photolithography, precise plasma or chemical wet etching, diffusion processes, and thin film evaporation. Electrical measurements were done by using an HP4156 parameter analyzer to measure several output voltage signals at one time while an illuminating the device with laser light. The current-voltage characteristics under different biasing conditions with an optical illumination condition were measured and showed characteristics similar to an nMOS transistor.

Description des différentes étapes de la conception d'un microprocesseur pour le contrôle des automatismes de sécurité, en particulier pour les systèmes de transport. Ce microprocesseur est autotestable, c'est-à-dire capable de détecter ses propres erreurs. La conception du circuit est basée sur les hypothèses de pannes au niveau analytique dans la technologie NMOS. Les blocs fonctionnels «Strongly Fault Secure» et les contrôleurs «Strongly Code Disjoint» sont à la base des circuits «Self-checking», dits autotestables. Le circuit COBRA démontre la faisabilité d'un microprocesseur autotestable. COBRA gère indépendamment 19 signaux différents, date des événements externes, mesure des fréquences, surveille 14 entrées logiques et possède 7 sorties indépendantes. Le programme d'application de COBRA est contenu dans une mémoire morte programmable externe de 16 Koctets adressés par 14 bits multiplexés sur le bus interne de 8 bits. COBRA contient également une liaison série, une mémoire à accès direct de 64 octets et 3 temporisateurs de 14 bits indépendants ainsi qu'une unité arithmétique et logique de 8 bits, COBRA exécute un jeu de 43 instructions

La phase de dessin des circuits intégrés est aujourd'hui le goulot d'étranglement entre la demande et la production. On présente le générateur automatique d'architectures pour circuits intégrés de filtrage numérique. La description d'un algorithme de filtrage assortie d'une contrainte «temps réel» est fournie au générateur. L'architecture optimisée en un temps requis est fournie sous la forme d'une partie opérative et d'un graphe d'états donnant le séquencement à appliquer

Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.