The design, construction and testing of a reverse-osmosis (PV-RO) desalination system for fresh water shortage area is presented. The system operates from salt water or brackish water and can be embedded in a renewable energy power supply system, since many fresh shortage areas are remote and isolated. Special attention is given to the energy efficiency of small-scale reverse osmosis desalination systems. Limitations of conventional control strategy using toggle control are presented. Based on this, an objective of creating a small-scale reverse osmosis desalination system was set out. Initially, the background information is presented. This includes the natural resources crisis and main desalination technologies and the viability of the integration with renewable energy source. A reverse osmosis (RO) desalination system was assembled and set up at the Curtin University of Technology, Perth, Western Australia Supervisor Control And Data Acquisition (SCADA) system was built using a Human Machine Interface software and a programmable logic controller (PLC). Instrumentation that included signal conditioners was made in analysis of the system characteristics. Initial testing of the system was conducted after the system design and configuration was accomplished. Testing results were used as a guideline for the development of the whole system. / Modelling and simulation of the system components in MATLABSimulink is presented, together with a discussion of the control systems modelling and design procedure, in which the aim was to improve the efficiency of the reverse osmosis system. Simulations show the designed reverse osmosis system with Proportional Integral and Derivative (PID) controller has better performance than other controllers. This consequently leads to a lower overall cost of the water, as well as reducing full maintenance cost of the electric drives in the reverse osmosis unit. Additionally, the configuration of the remote control system through General Package Radio System (GPRS) network is depicted. After the PID control algorithm was programmed into the Programmable Logic Controller (PLC), system experiments were carried out in short durations and long durations. System performance was monitored and experimental results prove that the new control strategy applied increase the water productivity and is able to improve the system efficiency up to 35%. Based on the data obtained from the simulations and experiments, Mundoo Island was chosen to be the location for a case study. The electric load profile of the island was derived from the Island Development Committee in Mundoo. / A water demand profile was created and modelled in Matlab to be the input of the reverse osmosis system. The electric load of the reverse osmosis system was generated from Matlab simulation. This result was entered in Hybrid Optimisation Model for Electric Renewables (HOMER) simulator. Having the designed RO unit as one of the electric loads, the entire remote area power supply (RAPS) system was tested in simulations which shows the energy cost is AUS$0.174 per kWh, lower than the Island Development Committee budget estimation of AUS$0.25 per kWh. The cost of the water treatment is very promising at AUS$0.77 per m3.

In this work, single stage power factor corrected AC/DC converters for LEDs / single stage Flyback converter having different configuration from the traditional Flyback and single stage SEPIC converter is investigated. The study involves analysis, circuit design, performance comparisons and implementation. The study covers LEDs / their developments, characteristics and state-of-art in this new technology. The circuits are investigated by means of computer simulations. Operating principles and operating modes are studied along with design calculations. After applying prototypes in laboratory, the simulation results and theoretical analyses are confirmed. The single stage Flyback converter has high voltage input (220-240 Vac), and the output feeds up to 216 HB-LEDs, with the ratings of 24 V, 3.25 A with 90 W. The single stage SEPIC converter with universal input (80-265 Vac) has an output that feeds 21 power LEDs, with 67 V, 0.30 and 20 W ratings.

Denna avhandling presenterar en undersökning av orsakerna och effekterna av timingosäkerhet i Sigma-Delta Analog-Digital-Omvandlare, med speciellt fokus på Sigma-Delta av den switchade kapacitanstypen. Det undersökta området för orsakerna till timingosäkerhet är digital klockgenerering och området för effekterna är sampling. Upplösningsnivån på analysen i detta arbete börjar på beteendenivå och slutar på transistornivå. Samplingskretsen är den intuitiva komponenten att söka i efter orsakerna till effekterna av timing-osäkerhet i en Analog-Digital-Omvandlare eftersom transformationen från reell tid till digital tid sker i samplingskretsen. Därför har prestandaeffekterna av timingosäkerhet i den typiska samplingskretsen för switchad kapacitans Sigma-Delta Analog-Digital-Omvandlare analyserats utförligt, modellerats och beskrivits i denna avhandling. Under analysprocessen har idéer om förbättrade samplingskretsar med naturlig tolerans mot timing-osäkerhet utvecklats och analyserats, och presenteras även. Två typer av förbättrade samplingstopologier presenteras: parallelsamplern och Sigma-Delta-samplern. Den första erhåller tolerans mot timing-osäkerhet genom att utnyttja ett teorem inom statistiken medan den andra är tolerant mot timing-osäkerhet p.g.a. spektral formning som trycker ut brus ur signalens frekvensband. Digital klockgenerering är ett fundamentalt steg i genereringen av multipla klocksignaler som behövs t.ex. i switchade kapacitansversioner av Sigma-Delta Analog-Digital-Omvandlare. Klockgeneratorkretsarna konverterar en tidsreferens, d.v.s. en klocksignal, som vanligen kommer från en faslåst loop till multipla tidsreferenser. De två typerna av klockgenereringskretsar som behandlas i denna avhandling används för att skapa två icke-överlappande klockor från en klocksignal. Processen som undersökts och beskrivits är hur matningsspänningsbrus och substratbrus omvandlas till timing-osäkerhet då en referenssignal passerar genom en av ovannämnda klockgenereringskretsar. Resultaten i denna avhandling har erhållits genom olika analystekniker. Modelleringarna och beskrivningarna har utförts från ett matematiskt och fysikaliskt perspektiv. Detta har fördelen av att kunna förutsäga prestandainfluenser som olika kretsparametrar har utan att behöva utföra datorsimuleringar. Svårigheterna med den matematiska och fysikaliska modelleringen är balansgången mellan olöslighet och överförenkling som måste hittas. Den andra infallsvinkeln är användandet av datorbaserade simuleringsverktyg både för beskrivnings- och verifieringsändamål. Simuleringsverktygen som använts är MATLAB och Spectre/Cadence. Som nämnts har deras syfte varit både som modell- och beskrivningsverifiering och även som ett sätt att erhålla kvantitativa resultat. Generellt talat bryter simuleringsverktyg den mentala kopplingen mellan resultat och diverse kretsparametrar och det kan vara svårt att uppnå en solid prestandaförståelse. Dock är det ibland bättre att erhålla ett prestandamått utan full förståelse än inget mått alls. / This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level. The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band. Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits. The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all. / QC 20100921

Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

Inom Försvarsmakten används motordrivna generatorer för att förse många förbandsenheter med elektricitet. Dagens bullriga och vibrerande elverk är idag möjliga att ersätta med tystare bränsleceller. På köpet erhålls en bättre ergonomi för alla som arbetar i hytter som strömförsörjs av elverk. I rapporten redovisas funktionen för olika typer av bränsleceller, vilka bränslen de använder sig av och hur dessa kan transporteras. Dessutom redovisas hur två elverk används och vilka förbättringar som kan åstadkommas vid byte till bränsleceller. Slutligen analyseras den militära nyttan med ett byte. / In the Armed Forces many units are provided with electricity from generators. It is now possible to replace noisy and vibrating generators used today with more quiet fuel cells. As a bonus, we obtain better ergonomics for those working in units powered by generators. This report describes the function of different types of fuel cells, what fuels they use and how they can be transported. Furthermore it shows how two generators are used and what improvements can be achieved when switching to fuel cells. Finally the military benefit of retrofitting is analyzed.

The Liquid-Salt-Cooled Very High-Temperature Reactor (LS-VHTR) was modeled using the neutronics analysis code SCALE6.0 and the thermal-hydraulics and kinetics modeling code RELAP5-3D with objective to devise, analyze, and evaluate the feasibility and stability of a start-up procedure for this reactor using natural circulation of the coolant and under the Loss Of Offsite Power (LOOP) conditions. This Generation IV reactor design has been studied by research facilities worldwide for almost a decade. While neutronics and thermal-hydraulics analyses have been previously performed to show the performance of the reactor during normal operation and for shutdown scenarios, no study has heretofore been published to examine the active or passive start-up of the reactor. The fuel temperature (Doppler) and coolant density coefficient of reactivity of the LS-VHTR were examined using the CSAS6 module of the SCALE6.0 code. Negative Doppler and coolant density feedback coefficients were calculated. Two initial RELAP5 simulations were run to obtain the steady-state conditions of the model and to predict the changes of the thermal-hydraulic parameters during the shutdown of the reactor. Next, a series of step reactivity additions to the core were simulated to determine how much reactivity can be inserted without jeopardizing safety and the stability of the core. Finally, a start-up procedure was developed, and the restart of the reactor with natural convection of the coolant was simulated. The results of the simulations demonstrated the potential of a passive start-up of the LS-VHTR.

As technology has scaled into nanometer regime, manufacturing variations have emerged as a major limiter of performance (timing) in VLSI circuits. Issues related to timing are addressed in the first part of the dissertation. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under uncertainty such as manufacturing variations. In this dissertation, we propose an efficient sparse-matrix framework for a path-based SSTA. In addition to an efficient framework for doing timing analysis, to improve the accuracy of the timing analysis one needs to address the accuracy of: waveform modeling, and gate delay modeling. We propose a technique based on Singular Value Decomposition (SVD) that accurately models the waveform in a timing analyzer. To improve the gate delay modeling, we propose a closed form expression based on the centroid of power dissipation. This new metric is inspired by our key observation that the Sakurai-Newton (SN) delay metric can be viewed as the centroid of current. In addition to accurately analyzing the timing of a chip, improving timing is another major concern. One way to improve timing is to scale down the threshold voltage (Vth). But scaling down increases the subthreshold leakage current exponentially. Sleep transistors have been proposed to reduce leakage current while maintaining performance. We propose a path-based algorithm to size the sleep transistor to reduce leakage while maintaining the required performance. In the second part of dissertation we address power grid and thermal issues that arise due to the scaling of integrated circuits. In the case of power grid simulation, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The transistor is modeled as a switch in series with an RC and the switch itself is modeled behaviorally. This model allows more accurate prediction of voltage drop compared to the current source model. In the case of thermal simulation, we address the issue of ignoring the nonlinearity of thermal conductivity in silicon. We found that ignoring the nonlinearity of thermal conductivity may lead to a temperature profile that is off by 10° C.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.

Intrinsically safe (IS) active power supplies subjected to certain transient load conditions can deliver power to a circuit at significantly higher levels than indicated on their nameplate ratings. During a transient load such as an intermittent short-circuit, energy is transferred from the power supply to the short-circuit and an electrical arc may form when the short-circuit is applied or removed. This poses a spark ignition risk as energy is transferred from the arc to the surrounding atmosphere. Currently various International and Australian Standards define the performance requirements for IS electrical apparatus. A duly accredited laboratory is required to establish the intrinsic safety compliance of an apparatus with the Standards. It involves an assessment of the apparatus and may include testing. The assessment of the apparatus determines adequate segregation, separation, construction, and selection of components. The tests performed on the apparatus include a temperature rise test and in some cases, the sparking potential of the circuit is tested using the spark test apparatus (STA). Testing the sparking potential of active power supplies to establish compliance adds significantly to the time and costs involved in establishing compliance. A new alternative assessment method is proposed in this report to augment or replace the testing phase of the compliance certification process for active power supplies. The proposed alternative assessment method (PAAM) is derived from a determination of the steady-state and transient output characteristics of the active power supply under consideration. Parameters such as peak output current, time constant of peak current decay, and the output voltages at these times are measured from the circuit's output characteristics. These measurements can subsequently be used to derive the topology and component values of an equivalent circuit. The resulting equivalent circuit is then considered like a linear power supply and the sparking potential can be determined using existing assessment methods. This thesis investigates in detail the equivalent circuit of a number of direct current (DC) active power supplies whose transient output characteristics exhibit predominantly capacitive behaviour. The results of the PAAM using the equivalent circuit are then compared with results achieved using the current testing procedure with a STA. A small sample of active power supplies is used to generate data from which a relationship between the current testing procedure and the PAAM can be established. The PAAM developed in this research project can be used as a pre-compliance check by designers, manufacturers, or IS testing stations. A failure of this test would indicate that the active power supply's sparking energy is not low enough to be regarded as intrinsically safe. The PAAM requires fewer resources to establish a result than the STA. The benefits of a simplified spark ignition test would flow on from designers and manufacturers to end users.