Ο στόχος της παρούσας διπλωματικής εργασίας είναι ο έλεγχος και αποκατάσταση της θερμοκρασίας και της υγρασίας από απόσταση σε ένα χώρο ο οποίος απαιτεί συγκεκριμένες τιμές των δύο παραπάνω μεγεθών. Ένας τέτοιος χώρος μπορεί να είναι μια αίθουσα χειρουργείου ή μια μονάδα εντατικής θεραπείας. Ανάλογα με τις επιθυμητές θερμοκρασίες που έχουν τεθεί, ενεργοποιούνται οι βάνες του θερμαντικού ή του ψυκτικού στοιχείου. Όταν η υγρασία του χώρου είναι κατώτερη της επιθυμητής, ενεργοποιείται η τρίοδος βάνα ατμού. Όταν η υγρασία του χώρου είναι υψηλότερη της επιθυμητής ενεργοποιείται η τρίοδος βάνα του ψυκτικού στοιχείου για επιπλέον ψύξη (αφύγρανση) και παράλληλα, αν χρειαστεί ενεργοποιεί και την τρίοδο βάνα του θερμαντικού στοιχείου για να διατηρήσει τη θερμοκρασία του χώρου στα επιθυμητά επίπεδα. Όλα αυτά υλοποιούνται με τη βοήθεια του PLC S7 300 όσο αφορά το λειτουργικό μέρος, της μονάδας CP 343-1 Lean για την επικοινωνία της εγκατάστασης από απόσταση μέσω ethernet, το LabVIEW 9.0 για την υλοποίηση του SCADA(Supervisory Control and Data Acquisition) και τέλος ο OPC SERVER της National instrument για την επικοινωνία του PLC S7 300 με το LabVIEW 9.0. / The scope of this thesis is the control and restoration of temperature and humidity from distance in environments which demand precise values of these two measurements. Such an environment can be an Operating Room or an Intensive Care Unit. The valves of the heating or the cooling element are activated according to the desired temperature. When room humidity is below the desired one, the dew three-port valve is activated. On the other hand when humidity is above the desired level the three-port valve of the cooling element is activated for further cooling (dehydration) and at the same time, if needed, it activates the three-port valve of the heating element to maintain the room temperature at the desired level. This is possible with the use of PLC S7 300, when it comes to the functional part, the CP 343-1 Lean unit for the distant communication of the installation through the use of Ethernet, the LabVIEW 9.0 for the implementation of the SCADA(Supervisory Control and Data Acquisition) and the OPC SERVER of the National Instrument for the communication of the PLC S7 300 with LabVIEW 9.0.

Αντικείμενο της παρούσας Διπλωματικής Εργασίας είναι η παρουσίαση, μελέτη και αξιολόγηση του Προγραμματιζόμενου Λογικού Ελεγκτή «OPTO 22 SNAP PAC». Στα πλαίσια της εργασίας και με τη χρήση του συγκεκριμένου PLC, αναπτύχθηκε μια σειρά προγραμμάτων αυτοματισμού, τα οποία ποικίλουν από στοιχειώδους αυτοματισμούς, όπως η λειτουργία ενός κινητήρα με θερμική προστασία, μέχρι πολύπλοκες εφαρμογές, όπως ο αυτοματισμός της λειτουργίας ενός υποσταθμού διανομής Μέσης Τάσης. Ακόμη, αναπτύχθηκε κι ένα σύστημα γραφικής απεικόνισης SCADA. Τα κεφάλαια 1,2,3,4,7 του παρόντος τεύχους αποτελούν ένα εγχειρίδιο χρήσης του PLC, καθώς στα κεφάλαια αυτά γίνεται παρουσίαση του υλικού και του λογισμικού με το οποίο συνοδεύεται, ενώ γίνεται επεξήγηση βήμα-βήμα της εγκατάστασης του υλικού και του τρόπου λειτουργίας του λογισμικού. Στο κεφάλαιο 5 παρουσιάζονται τα 22 προγράμματα αυτοματισμού που αναπτύχθηκαν. Έπειτα, στο κεφάλαιο 6 γίνεται σύγκριση του περιβάλλοντος προγραμματισμού του OPTO 22 SNAP PAC με τις γλώσσες προγραμματισμού που έχουν θεσπιστεί από το πρότυπο IEC61131 της διεθνούς ηλεκτροτεχνικής επιτροπής. Ακολούθως, στο κεφάλαιο 8 παρουσιάζεται το σύστημα SCADA που αναπτύχθηκε καθώς επίσης και το αντίστοιχο πρόγραμμα αυτοματισμού της εφαρμογής. Τέλος, γίνεται σχολιασμός των δυνατοτήτων του OPTO 22 SNAP PAC και αναφορά σε πλεονεκτήματα και μειονεκτήματά του. / The following thesis' purpose is to present, study and evaluate the Programmable Logic Controller "OPTO 22 SNAP PAC". During this thesis, a number of automation programms were developed which vary between simple applications such as the automatic function of a motor using two buttons (start-stop), and more complicated applications such as the design of the automatic protection of an AC/AC High Voltage Transformer. Furthermore, A SCADA project was developed. At chapters 1,2,3,4,7 the reader can find the presentation of the product and a kind of manual for the PLC. Chapter 5 is the presentation of the automation programms. At chapter 6, there is a comparison between PAC Control Basic and SFC. Then, at chapter 8 the SCADA project is presented. Finally, there is a reference of positives and negatives of OPTO 22 SNAP PAC.

Na atualidade, as redes públicas de comunicação de dados representam uma nova oportunidade para a aplicação das tecnologias IEEE 802 (baseadas na tecnologia Ethernet). Tanto nas redes de acesso, como nas redes metropolitanas e de núcleo, existe uma crescente demanda pela instalação de equipamentos com grande número de interfaces Ethernet. Em alguns casos, opta-se por equipamentos capazes de emular os serviços das tecnologias legadas ATM/SDH sobre Ethernet e viceversa. Nesse sentido, novos protocolos e novas formas de transmissão de dados utilizando a tecnologia Ethernet estão surgindo para consolidar a convergência das redes de comutação de circuitos (infraestrutúra legada) e as redes de comutação de pacotes; com a ideia de constituir uma rede mais homogênea, flexível e de baixo custo. Um claro exemplo é a adessão dos protocolos de Operação, Administração e Manuntenção (OAM) nas redes Ethernet, os quais permitem um nível de controle semelhante ao de tecnologias como ATM e SDH. OAM possibilita a monitoração de falhas na rede, a configuração e o acompanhamento dos eventos de segurança, assim como também a contabilização de tráfego por assinante; permitindo desta forma o atendimento de diferentes SLAs (Service-Level Agreements) de clientes. Para que isto seja uma realidade, é muito importante reforçar o controle da borda que delimita a rede do cliente final da rede pública. Com esse fim, estão surgindo normas como a IEEE P802.1aj, que define um dispositivo de demarcação de rede que serve como entidade controladora de serviços entre o provedor e o cliente final; sendo sua principal característica o suporte OAM no enlace com o provedor de serviços. Este dispositivo - conhecido comercialmente como Ethernet Demarcation Device (EDD)- é o foco do presente trabalho. Este trabalho tem como objetivo principal desenvolver arquiteturas System-on-a-Programable Chip (SoPC) para um EDD de duas portas, partindo do desenvolvimento de módulos de propriedade intelectual (IP). Foram projetadas duas arquiteturas de EDD, as quais permitem o encaminhamento de pacotes entre duas portas Ethernet e incorporam um processador MicroBlaze para implementação Software do protocolo OAM, segundo a norma IEEE 802.3ah. Como resultado, foram elaborados 7 módulos IP: Módulo Fast Ethernet MAC (FEMAC), Módulo Gigabit Ethernet MAC (GEMAC), Módulo Packet FIFO, Módulo OAM Ethernet, Módulo MII Managment (MIIM), Módulo PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) e Módulo Bit-Error Rate Tester (BERT). Todos os módulos foram descritos em VHDL e logo sintetizados para um dispositivo FPGA da família Virtex-II Pro da Xilinx, quanto para standard-cells utilizando a tecnologia CMOS AMS 0.35μm únicamente nos Módulos FEMAC e GEMAC. Os resultados de síntese mostram que o Módulo MIIM e o Módulo PHY1000X possuim um melhor aproveitamento de recursos de área que seus equivalentes disponíveis no OpenCores e no CoreGen da Xilinx, respectivamente. As arquiteturas SoPC foram prototipadas sobre a placa de desenvolvimento AVNET Virtex-II Pro, a qual permite comunicação com dispositivos de rede através de interfaces elétricas e ópticas. Finalmente, é proposta uma metodologia de validação física das arquiteturas alvo para estas atenderem o regime de vazão máxima (1Gbit/s ou 100Mbit/s), assim como também testes de conformidade como os definidos pela norma IEEE 802.3. / Nowadays, public networks represent a new opportunity for the application of IEEE 802 technologies, which have their basis on Ethernet Technology. In both Access and Metropolitan and Core networks there is a growing demand for the installation of equipments with a large number of Ethernet interfaces. In some cases, equipments capable of emulating the services of the ATM/SDH legacy technologies over Ethernet (and vice versa) are chosen. In this manner, new protocols and data transmission forms using Ethernet technology are emerging in order to consolidate the convergence of circuit switching networks (traditional infrastructure) and packet switching networks; with the common objetive of constituting a more uniform, flexible, low-cost network. A good example is the incorporation of Operation, Administration and Maintenance (OAM) protocols in Ethernet networks, which allow a control level similar to that one of technologies such as ATM and SDH. OAM allows the monitoring of network fails, the configuration and tracking the security events, as well as the counting of traffic per client in a way that permits to attend several SLAs (Service-Level Agreements). In order to bring this to reality, it is critical to reinforce the control of the edge which limits the client network from the public networks. With this aim, standards such as IEEE P802.1aj are emerging; this standard defines a network demarcation device, which is used as a service controlling entity between the provider and the end customer, having as main feature the OAM support in the link with the service provider. This work is focused on this device, commercially known as Ethernet Demarcation Device (EDD). The principal objective of this work is to develop SoPC (System-on-a-Programable chip) architectures for an EDD, starting from the development of Intellectual Property Cores (IP). Two EDD architectures were designed, which allow the packet forwarding between two Ethernet interfaces and incorporate a Soft processor Microblaze for the SW implementation of the OAM protocol according to the standard IEEE802.3ah. As a result, eight IP cores were elaborated: Soft IP Core Fast Ethernet MAC (FEMAC), Soft IP Core Gigabit Ethernet MAC (GEMAC), Soft IP Core Packet FIFO, Soft IP Core OAM Ethernet, Soft IP Core MII Managment (MIIM), Soft IP Core PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) and the Soft IP Core Bit-Error Rate Tester (BERT). All IP modules were described in VHDL and then synthesized for the FPGA Xilinx Virtex-II Pro device, as well as for standard-cells using the CMOS AMS 0.35um technology for the modules FEMAC and GEMAC. The synthesis results show that the module MIIM and module PHY1000X have a better use of the area resources than the ones available in OpenCores and CoreGen of Xilinx respectively. The SoPC architectures were prototyped on AVNET Virtex-II Pro Development kit Board, which allows communication with network devices through electrical and optical interfaces. Finally, we propose a validation methodology of both architecture so these are able to attend a maximum throughput regimen (1Gbit/s ou 100Mbit/s), as well as appropriate levels of approval with what standard IEEE 802.3 defines.

Na atualidade, as redes públicas de comunicação de dados representam uma nova oportunidade para a aplicação das tecnologias IEEE 802 (baseadas na tecnologia Ethernet). Tanto nas redes de acesso, como nas redes metropolitanas e de núcleo, existe uma crescente demanda pela instalação de equipamentos com grande número de interfaces Ethernet. Em alguns casos, opta-se por equipamentos capazes de emular os serviços das tecnologias legadas ATM/SDH sobre Ethernet e viceversa. Nesse sentido, novos protocolos e novas formas de transmissão de dados utilizando a tecnologia Ethernet estão surgindo para consolidar a convergência das redes de comutação de circuitos (infraestrutúra legada) e as redes de comutação de pacotes; com a ideia de constituir uma rede mais homogênea, flexível e de baixo custo. Um claro exemplo é a adessão dos protocolos de Operação, Administração e Manuntenção (OAM) nas redes Ethernet, os quais permitem um nível de controle semelhante ao de tecnologias como ATM e SDH. OAM possibilita a monitoração de falhas na rede, a configuração e o acompanhamento dos eventos de segurança, assim como também a contabilização de tráfego por assinante; permitindo desta forma o atendimento de diferentes SLAs (Service-Level Agreements) de clientes. Para que isto seja uma realidade, é muito importante reforçar o controle da borda que delimita a rede do cliente final da rede pública. Com esse fim, estão surgindo normas como a IEEE P802.1aj, que define um dispositivo de demarcação de rede que serve como entidade controladora de serviços entre o provedor e o cliente final; sendo sua principal característica o suporte OAM no enlace com o provedor de serviços. Este dispositivo - conhecido comercialmente como Ethernet Demarcation Device (EDD)- é o foco do presente trabalho. Este trabalho tem como objetivo principal desenvolver arquiteturas System-on-a-Programable Chip (SoPC) para um EDD de duas portas, partindo do desenvolvimento de módulos de propriedade intelectual (IP). Foram projetadas duas arquiteturas de EDD, as quais permitem o encaminhamento de pacotes entre duas portas Ethernet e incorporam um processador MicroBlaze para implementação Software do protocolo OAM, segundo a norma IEEE 802.3ah. Como resultado, foram elaborados 7 módulos IP: Módulo Fast Ethernet MAC (FEMAC), Módulo Gigabit Ethernet MAC (GEMAC), Módulo Packet FIFO, Módulo OAM Ethernet, Módulo MII Managment (MIIM), Módulo PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) e Módulo Bit-Error Rate Tester (BERT). Todos os módulos foram descritos em VHDL e logo sintetizados para um dispositivo FPGA da família Virtex-II Pro da Xilinx, quanto para standard-cells utilizando a tecnologia CMOS AMS 0.35μm únicamente nos Módulos FEMAC e GEMAC. Os resultados de síntese mostram que o Módulo MIIM e o Módulo PHY1000X possuim um melhor aproveitamento de recursos de área que seus equivalentes disponíveis no OpenCores e no CoreGen da Xilinx, respectivamente. As arquiteturas SoPC foram prototipadas sobre a placa de desenvolvimento AVNET Virtex-II Pro, a qual permite comunicação com dispositivos de rede através de interfaces elétricas e ópticas. Finalmente, é proposta uma metodologia de validação física das arquiteturas alvo para estas atenderem o regime de vazão máxima (1Gbit/s ou 100Mbit/s), assim como também testes de conformidade como os definidos pela norma IEEE 802.3. / Nowadays, public networks represent a new opportunity for the application of IEEE 802 technologies, which have their basis on Ethernet Technology. In both Access and Metropolitan and Core networks there is a growing demand for the installation of equipments with a large number of Ethernet interfaces. In some cases, equipments capable of emulating the services of the ATM/SDH legacy technologies over Ethernet (and vice versa) are chosen. In this manner, new protocols and data transmission forms using Ethernet technology are emerging in order to consolidate the convergence of circuit switching networks (traditional infrastructure) and packet switching networks; with the common objetive of constituting a more uniform, flexible, low-cost network. A good example is the incorporation of Operation, Administration and Maintenance (OAM) protocols in Ethernet networks, which allow a control level similar to that one of technologies such as ATM and SDH. OAM allows the monitoring of network fails, the configuration and tracking the security events, as well as the counting of traffic per client in a way that permits to attend several SLAs (Service-Level Agreements). In order to bring this to reality, it is critical to reinforce the control of the edge which limits the client network from the public networks. With this aim, standards such as IEEE P802.1aj are emerging; this standard defines a network demarcation device, which is used as a service controlling entity between the provider and the end customer, having as main feature the OAM support in the link with the service provider. This work is focused on this device, commercially known as Ethernet Demarcation Device (EDD). The principal objective of this work is to develop SoPC (System-on-a-Programable chip) architectures for an EDD, starting from the development of Intellectual Property Cores (IP). Two EDD architectures were designed, which allow the packet forwarding between two Ethernet interfaces and incorporate a Soft processor Microblaze for the SW implementation of the OAM protocol according to the standard IEEE802.3ah. As a result, eight IP cores were elaborated: Soft IP Core Fast Ethernet MAC (FEMAC), Soft IP Core Gigabit Ethernet MAC (GEMAC), Soft IP Core Packet FIFO, Soft IP Core OAM Ethernet, Soft IP Core MII Managment (MIIM), Soft IP Core PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) and the Soft IP Core Bit-Error Rate Tester (BERT). All IP modules were described in VHDL and then synthesized for the FPGA Xilinx Virtex-II Pro device, as well as for standard-cells using the CMOS AMS 0.35um technology for the modules FEMAC and GEMAC. The synthesis results show that the module MIIM and module PHY1000X have a better use of the area resources than the ones available in OpenCores and CoreGen of Xilinx respectively. The SoPC architectures were prototyped on AVNET Virtex-II Pro Development kit Board, which allows communication with network devices through electrical and optical interfaces. Finally, we propose a validation methodology of both architecture so these are able to attend a maximum throughput regimen (1Gbit/s ou 100Mbit/s), as well as appropriate levels of approval with what standard IEEE 802.3 defines.

Na atualidade, as redes públicas de comunicação de dados representam uma nova oportunidade para a aplicação das tecnologias IEEE 802 (baseadas na tecnologia Ethernet). Tanto nas redes de acesso, como nas redes metropolitanas e de núcleo, existe uma crescente demanda pela instalação de equipamentos com grande número de interfaces Ethernet. Em alguns casos, opta-se por equipamentos capazes de emular os serviços das tecnologias legadas ATM/SDH sobre Ethernet e viceversa. Nesse sentido, novos protocolos e novas formas de transmissão de dados utilizando a tecnologia Ethernet estão surgindo para consolidar a convergência das redes de comutação de circuitos (infraestrutúra legada) e as redes de comutação de pacotes; com a ideia de constituir uma rede mais homogênea, flexível e de baixo custo. Um claro exemplo é a adessão dos protocolos de Operação, Administração e Manuntenção (OAM) nas redes Ethernet, os quais permitem um nível de controle semelhante ao de tecnologias como ATM e SDH. OAM possibilita a monitoração de falhas na rede, a configuração e o acompanhamento dos eventos de segurança, assim como também a contabilização de tráfego por assinante; permitindo desta forma o atendimento de diferentes SLAs (Service-Level Agreements) de clientes. Para que isto seja uma realidade, é muito importante reforçar o controle da borda que delimita a rede do cliente final da rede pública. Com esse fim, estão surgindo normas como a IEEE P802.1aj, que define um dispositivo de demarcação de rede que serve como entidade controladora de serviços entre o provedor e o cliente final; sendo sua principal característica o suporte OAM no enlace com o provedor de serviços. Este dispositivo - conhecido comercialmente como Ethernet Demarcation Device (EDD)- é o foco do presente trabalho. Este trabalho tem como objetivo principal desenvolver arquiteturas System-on-a-Programable Chip (SoPC) para um EDD de duas portas, partindo do desenvolvimento de módulos de propriedade intelectual (IP). Foram projetadas duas arquiteturas de EDD, as quais permitem o encaminhamento de pacotes entre duas portas Ethernet e incorporam um processador MicroBlaze para implementação Software do protocolo OAM, segundo a norma IEEE 802.3ah. Como resultado, foram elaborados 7 módulos IP: Módulo Fast Ethernet MAC (FEMAC), Módulo Gigabit Ethernet MAC (GEMAC), Módulo Packet FIFO, Módulo OAM Ethernet, Módulo MII Managment (MIIM), Módulo PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) e Módulo Bit-Error Rate Tester (BERT). Todos os módulos foram descritos em VHDL e logo sintetizados para um dispositivo FPGA da família Virtex-II Pro da Xilinx, quanto para standard-cells utilizando a tecnologia CMOS AMS 0.35μm únicamente nos Módulos FEMAC e GEMAC. Os resultados de síntese mostram que o Módulo MIIM e o Módulo PHY1000X possuim um melhor aproveitamento de recursos de área que seus equivalentes disponíveis no OpenCores e no CoreGen da Xilinx, respectivamente. As arquiteturas SoPC foram prototipadas sobre a placa de desenvolvimento AVNET Virtex-II Pro, a qual permite comunicação com dispositivos de rede através de interfaces elétricas e ópticas. Finalmente, é proposta uma metodologia de validação física das arquiteturas alvo para estas atenderem o regime de vazão máxima (1Gbit/s ou 100Mbit/s), assim como também testes de conformidade como os definidos pela norma IEEE 802.3. / Nowadays, public networks represent a new opportunity for the application of IEEE 802 technologies, which have their basis on Ethernet Technology. In both Access and Metropolitan and Core networks there is a growing demand for the installation of equipments with a large number of Ethernet interfaces. In some cases, equipments capable of emulating the services of the ATM/SDH legacy technologies over Ethernet (and vice versa) are chosen. In this manner, new protocols and data transmission forms using Ethernet technology are emerging in order to consolidate the convergence of circuit switching networks (traditional infrastructure) and packet switching networks; with the common objetive of constituting a more uniform, flexible, low-cost network. A good example is the incorporation of Operation, Administration and Maintenance (OAM) protocols in Ethernet networks, which allow a control level similar to that one of technologies such as ATM and SDH. OAM allows the monitoring of network fails, the configuration and tracking the security events, as well as the counting of traffic per client in a way that permits to attend several SLAs (Service-Level Agreements). In order to bring this to reality, it is critical to reinforce the control of the edge which limits the client network from the public networks. With this aim, standards such as IEEE P802.1aj are emerging; this standard defines a network demarcation device, which is used as a service controlling entity between the provider and the end customer, having as main feature the OAM support in the link with the service provider. This work is focused on this device, commercially known as Ethernet Demarcation Device (EDD). The principal objective of this work is to develop SoPC (System-on-a-Programable chip) architectures for an EDD, starting from the development of Intellectual Property Cores (IP). Two EDD architectures were designed, which allow the packet forwarding between two Ethernet interfaces and incorporate a Soft processor Microblaze for the SW implementation of the OAM protocol according to the standard IEEE802.3ah. As a result, eight IP cores were elaborated: Soft IP Core Fast Ethernet MAC (FEMAC), Soft IP Core Gigabit Ethernet MAC (GEMAC), Soft IP Core Packet FIFO, Soft IP Core OAM Ethernet, Soft IP Core MII Managment (MIIM), Soft IP Core PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) and the Soft IP Core Bit-Error Rate Tester (BERT). All IP modules were described in VHDL and then synthesized for the FPGA Xilinx Virtex-II Pro device, as well as for standard-cells using the CMOS AMS 0.35um technology for the modules FEMAC and GEMAC. The synthesis results show that the module MIIM and module PHY1000X have a better use of the area resources than the ones available in OpenCores and CoreGen of Xilinx respectively. The SoPC architectures were prototyped on AVNET Virtex-II Pro Development kit Board, which allows communication with network devices through electrical and optical interfaces. Finally, we propose a validation methodology of both architecture so these are able to attend a maximum throughput regimen (1Gbit/s ou 100Mbit/s), as well as appropriate levels of approval with what standard IEEE 802.3 defines.

Orientador: João Maurício Rosário / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica / Made available in DSpace on 2018-08-17T01:25:49Z (GMT). No. of bitstreams: 1 CastilloEstepa_RicardoAndres_M.pdf: 7409956 bytes, checksum: 80c4bd559f383881e7ad078cc2d08dad (MD5) Previous issue date: 2010 / Resumo: Este trabalho propõe uma arquitetura genérica de supervisão e comando para uma plataforma automatizada de experimentação modular com capacidade de utilização remota, concebida para apoiar e complementar os processos de formação e pesquisa em Automação Industrial e Robótica, descrevendo sua concepção, modelagem dinâmica e implementação hardware - software. A integração de tecnologias e dispositivos industriais existentes no mercado (Controladores Lógicos Programáveis - CLP, diversos tipos de sensores e atuadores industriais, processamento de imagens, sistemas supervisórios e dispositivos robóticos de movimentação) em uma única plataforma implementada através de uma arquitetura modular de Sistema Automatizado de Produção Colaborativo (CSAP/ADACOR) permite que alunos e pesquisadores possam interatuar com essas tecnologias realizando atividades de modo a automatizar, supervisar e comandar um processo completo de produção. Uma plataforma desenvolvida utilizando esta arquitetura genérica permite aos estudantes e pesquisadores trabalhar dentro de um ambiente educacional, mas que retrata a maioria dos aspectos encontrados em um Sistema Automatizado de Manufatura real, tais como Integração Tecnológica, Redes de Comunicação, Controle de Processos e Gestão da Produção. Além disso, é possível realizar o controle e supervisão do processo completo que ocorre na plataforma automatizada por meio de uma conexão remota que utiliza a internet - WEBLAB (Laboratório Remoto); possibilitando que usuários e grupos em diferentes lugares possam utilizar a plataforma e compartilhar informação rapidamente. Pode-se destacar também que as características de Modularidade e Flexibilidade da plataforma permitem futuras modificações tanto do software quanto do hardware da mesma / Abstract: This work proposes a generic supervisory and command architecture for an experimentation modular automated platform equipped with remote access capacities which is conceived with the aim of improve training and research processes on Automation and Robotics, this study describes the platform's design, dynamic modeling and implementation stages. The technologic and industrial devices integration (Programmable Logic Controllers - PLC, several types of sensors and actuators, image processing, supervisory systems and robotic manipulation devices) in a single platform which is implemented following a modular Collaborative Automatic Production System (CAPS/ADACOR) architecture allows students and researchers to Interact with it by means of doing practices in order to successfully automate, supervise and manage a complete production process. Therefore, class acquired theoretical concepts are supported so improving user's professional skills. A platform developed using the here proposed generic structure allows users to work within an educational environment coping with most of the encountered aspects in a real Manufacturing Automation System, such as Technologic Integration, Communication Networks, Process Control and Production Management. Furthermore it is possible to command the entire assembly process taking place at the platform by a remote network connection using the internet - WEBLAB (Remote Laboratory), enabling individual users and groups in different places in order to use the platform and quickly interchange information. In addition it is important to outstand that both the Modularity and Flexibility of the platform can allow readily any further hardware or software enhancement / Mestrado / Mecanica dos Sólidos e Projeto Mecanico / Mestre em Engenharia Mecânica

The majority of the power generated today is produced using fossil fuels,emitting carbon dioxide and other pollutants every second. Also, fossil fuels will eventually run out. For the increasing worldwide energy demand, the use f reliable and environmentally beneficial natural energy sources is one of the biggest challenges. Alongside wind and water, the solar energy which is clean, CO2-neutral and limitless, is our most valuable resource. Concentrated solar power (CSP) is becoming one of the excellent alternative sources for the power industry. The successful implementation of this technology requires the efficient design of tracking and operation system of the CSP solar plants. A detailed analysis of components needed for the design of cost-effective and optimum tracker for CSP solar systems is required for the power plant modeling, which is the primary subject of this thesis. A comprehensive tracking and operating system of a parabolic trough solar power plant was developed focusing primarily on obtaining optimum and cost effective design through the simplified methodology of this work. This new model was implemented for a 50 kWe parabolic trough solar power plant at University of South Florida, Tampa.

The Target Positioning Sensor (TPS) is used by cranes to locate containers in ports and on cargo ships. The reliability of the communication network between the TPS and the Programmable Logic Controller (PLC) is important to optimise the productivity of the container terminal. Lost data messages between the network devices will lead to delays and production loss for the terminal. The main goal of this thesis project is to make the Ethernet-based network between the TPS and the PLC more reliable. The current sensor network protocol uses the User Datagram Protocol (UDP), and the project aims to replace that with the Transport Control Protocol (TCP). This includes designing a new message handling application and performing case studies on how to best handle compatibility issues between the TPS and the PLC, to improve the longevity of the application. The case studies led to considering an adaptable behaviour toward future software updates in different parts of the network. An application which used TCP to communicate between a PC and a PLC was developed, intended to be used as a reference during future integration into the actual sensor network. The TCP application works but needs to be improved before being implemented in a real system. In addition, the project also looked into Time-Sensitive Networking, which is a method of increasing link capacity and reliability in time-sensitive network implementations. This was done through a literature study on the IEEE Time-Sensitive Networking Standard, which showed that the application of the standard could be beneficial if more sensors are added to the network of if the sampling frequency of the TPS is increased.

This diploma thesis is engaged in implementations of algorithms for signal filtering in the field programmable gate array utilising the C and ImpulseC programming language. It is focused on one-dimensional FIR and IIR filters and also two-dimensional such as convolution and Sobel's operator. Moreover, evaluations of these filter algorithms are included.

The main aim of this master´s thesis is to launch a chain tools storage. The main intention of this work is creation of a control program for the programmable logic controller and HMI (Human Machine Interface). My master´s thesis contains optimization of location tools in chain tools storage. Program part consists of software modules which contain different algorithms (optimization of speed of start-up beds, beds approaching the shortest path and optimal deployment tools).