abstract: RF convergence of radar and communications users is rapidly becoming an issue for a multitude of stakeholders. To hedge against growing spectral congestion, research into cooperative radar and communications systems has been identified as a critical necessity for the United States and other countries. Further, the joint sensing-communicating paradigm appears imminent in several technological domains. In the pursuit of co-designing radar and communications systems that work cooperatively and benefit from each other's existence, joint radar-communications metrics are defined and bounded as a measure of performance. Estimation rate is introduced, a novel measure of radar estimation information as a function of time. Complementary to communications data rate, the two systems can now be compared on the same scale. An information-centric approach has a number of advantages, defining precisely what is gained through radar illumination and serves as a measure of spectral efficiency. Bounding radar estimation rate and communications data rate jointly, systems can be designed as a joint optimization problem. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

La protection contre les décharges électrostatiques (ESD) est un fait necessaire dans chaque circuit intégré. Elle se fait par le déploiement sur la puce d'un réseau de dispositifs spéciaux, à côtés des éléments fonctionnels. La demande pour des améliorations en continu dans la conception et la simulation de l'ESD apporte le besoin de modèles nouveaux et plus précises. La SCR (« Silicon Controlled Rectifier ») est l'un des dispositifs les plus efficaces de protection contre l'ESD. Un nouveau modèle électrique, qui peut être utilisé pour évaluer les structures de protection complexe dont il fait partie, a été développé au cours de cette thèse. Construit avec une forte relation entre les phénomènes physiques et ses équations, il a été parametrisé geometriquement, offrant la possibilité d'adapter et d'optimiser le dispositif selon le niveau de protection nécessaire. Par ailleurs, une étude à haute fréquence sur le SCR et la diode de protection ESD a été réalisé, conduisant à un modèle capable de prédire l'impact de ces dispositifs ont sur le circuit protégé. / Electrostatic discharge (ESD) protection is a must in every integrated circuit. It is done by deploying a network of special devices on-chip, alongside the functional elements. The demand for continuously improvements in ESD design and simulations brings the need of new and more accurate scalable models. The SCR (silicon controlled rectifier) is one of the most efficient ESD protection devices. A new electrical model, that can be used to evaluate the complex protection structures of which it is part of, was developed during this thesis. Built with a strong relation between the physical phenomena and its equations, it was rendered scalable, offering the possibility of tailoring and optimizing the device according to the needed protection level. Moreover, a high-frequency study on the SCR and the ESD protection diode was carried out, leading to a model able to predict the impact these devices have on the protected circuit.

abstract: This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design was successful, and used in a commercially available product. / Dissertation/Thesis / M.S. Electrical Engineering 2012

abstract: Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test times, which complicates load-board design, debug, and diagnosis. Second, high frequency operation necessitates the use of expensive equipment, resulting in higher per second test time cost compared with mixed-signal or digital circuits. Moreover, in terms of the non-recurring engineering cost, the need to measure complex specfications complicates the test development process and necessitates a long learning process for test engineers. Test time is dominated by changing and settling time for each test set-up. Thus, single set-up test solutions are desirable. Loop-back configuration where the transmitter output is connected to the receiver input are used as the desirable test set- up for RF transceivers, since it eliminates the reliance on expensive instrumentation for RF signal analysis and enables measuring multiple parameters at once. In-phase and Quadrature (IQ) imbalance, non-linearity, DC offset and IQ time skews are some of the most detrimental imperfections in transceiver performance. Measurement of these parameters in the loop-back mode is challenging due to the coupling between the receiver (RX) and transmitter (TX) parameters. Loop-back based solutions are proposed in this work to resolve this issue. A calibration algorithm for a subset of the above mentioned impairments is also presented. Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. EVM is analytically related to system impairments, which are typically measured in a production test i environment. Thus, EVM test can be eliminated from the test list if the relations between EVM and system impairments are derived independent of the circuit implementation and manufacturing process. In this work, the focus is on the WLAN standard, and deriving the relations between EVM and three of the most detrimental impairments for QAM/OFDM based systems (IQ imbalance, non-linearity, and noise). Having low cost test techniques for measuring the RF transceivers imperfections and being able to analytically compute EVM from the measured parameters is a complete test solution for RF transceivers. These techniques along with the proposed calibration method can be used in improving the yield by widening the pass/fail boundaries for transceivers imperfections. For all of the proposed methods, simulation and hardware measurements prove that the proposed techniques provide accurate characterization of RF transceivers. / Dissertation/Thesis / Ph.D. Electrical Engineering 2013

Abstract This thesis studies the level of performance achievable using today's standard IC processes in the integrated RF subcircuits of the modern GSM base station. The thesis concentrates on those circuit functions, i.e. I/Q modulators, variable gain amplifiers and frequency synthesizers, most relevant for integration in the base station environment as pinpointed by studying the receiver/transmitter architectures available today. Several RF integrated circuits have been designed, fabricated and their level of performance measured. All main circuits were fabricated in a standard double-metal double-poly 1.2 and 0.8 μm BiCMOS process. Key circuit structures and their measured properties are: 90° phase shifter with ±1° phase error with VCC = 4.5…5.5 V and T = -10…+85 °C, I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz (2.0 mm × 2.0 mm, 100 mA, 5.0 V) with LO suppression of 38 dBc and image rejection of 41 dBc, temperature compensated DC to 1.5 GHz variable gain amplifier (1.15 mm × 2.00 mm, 100 mA, 5.0 V) with a linear 50 dB gain adjustment range, maximum gain of 18.5 dB and gain variation of 1 dB up to 700 MHz over the whole operating conditions range of VCC = 4.5…5.5 V and T = -10…+85 °C, a complete bipolar semicustom synthesizer (90…122 mA, 5.0 V) and two complete full-custom BiCMOS synthesizer chips including all building blocks of a PLL-based synthesizer except for the voltage controlled oscillator and the loop filter. The synthesizers include circuit structures such as ∼2 GHz multi-modulus divider and low-noise programmable phase detector/charge pump (18.7 pA/√Hz at Iout = 500 μA) and have an exemplar phase noise performance of -110 dBc/Hz at 200 kHz offset. One of the main problems of the integer-N PLL based synthesizer when used in a multichannel telecommunications system is the level of spurious signals at the output, when the synthesizer is optimised for fast frequency switching. Therefore, a method using only two current pulses to make the frequency step response of the loop faster, thus allowing a narrower loop bandwidth to be used for additional spur suppression, is proposed. The operation of the proposed speed-up method is analysed mathematically and verified by measurements of an existing RF-IC synthesizer operating at 800 MHz. Measurements show that simple current pulses can be used to speed up the channel switching of a practical RF synthesizer having a frequency step time in the tens of μs range. In the example, a 7.65 MHz frequency step was made seven times faster using the proposed method.

Abstract In the interest of improving reliability, electrical monitoring methods were utilized to observe the degradation of electronics interconnections while simultaneously characterizing accelerated testing-induced changes in test structures by means of optical examination, X-ray, scanning acoustic microscopy and scanning electron microscopy. To improve the accuracy of lifetime prediction for the PCSB interconnections investigated in this work, a modified Engelmaier’s solder joint lifetime prediction model was recalibrated. The results show that with most of the presented lead-free (SAC387, SAC405, SAC-In) solder and structure combinations with a large global thermal mismatch (ΔCTE > 10 ppm/°C), lifetime was adequate in the presented TCT ranges of 0‒100 °C and −40‒125 °C, while the amount of non-preferred crack types, i.e. ceramic cracks, was minimized. Degradation of interconnections was characterized using RF measurements both during TCT and intermittently during TCT breaks. A grounded coplanar waveguide was arranged either in a straight back-to-back configuration or together with a filter module with a passband at 22‒24 GHz—both with two transitions—and characterized during cycling breaks up to 25 GHz and 30 GHz, respectively. Besides off-cycle measurements, in-cycle measurements were done on an antenna structure with an in-band at 10‒11 GHz, up to 14 GHz. The results show that the signal response was initially affected at some frequencies as short-duration (< 1 s) glitches in the monitored signal when measured during cycling in 0‒100 °C TCT. Later on the degradation could be observed in the whole frequency band as TCT was continued. Development of the semi-empirical lifetime prediction model for PCSB interconnections showed the temperature range dependency of the correction term to be a second order polynomial instead of a logarithmic one. For components with PCSB BGA, promising prediction results were achieved which differed from the realized lifetime by less than 0.5% at best. / Tiivistelmä Elektroniikkaliitosten rikkoontumisen seurantaan tarkoitettuja sähköisiä monitorointimenetelmiä kehitettiin samanaikaisesti karakterisoimalla testauksella liitoksiin aikaansaatuja muutoksia optisesti, akustisella mikroskoopilla sekä röntgen- ja pyyhkäisyelektronimikroskoopeilla. Liitosten eliniän ennustamiseen soveltuva muokattu Engelmaierin malli kalibroitiin PCSB-liitosten elinikäennusteen tarkkuuden parantamiseksi. Tulosten perusteella useimmille tässä työssä käytetyille lyijyttömille (SAC387, SAC405, SAC-In) juotteille ja suuren termisen epäsovituksen (ΔCTE > 10 ppm/°C) rakenneyhdistelmille eliniät lämpösyklaustesteissä 0‒100 °C ja −40‒125 °C alueilla olivat riittävät ja haitallisimpien murtumien, eli keraamimurtumien, määrä saatiin minimoiduksi. RF-mittauksia käytettiin liitosten vikaantumisen seurantaan sekä lämpösyklauksen aikana että syklausten välillä. Maadoitettua koplanaarista aaltojohtoa käytettiin joko suoraan perättäiskytkennässä tai suodatinmoduulin kanssa, jonka päästökaista oli 22–24 GHz. Rakenteet karakterisoitiin syklausten välillä 25 GHz ja 30 GHz asti tässä järjestyksessä. Näiden mittausten lisäksi 10–11 GHz kaistalla toimivaa antennirakennetta karakterisoitiin syklauksen aikana 14 GHz asti. Tulokset osoittavat, että signaalivasteen muutos ilmenee aluksi joillakin taajuuksilla lyhyinä, alle 1 s mittaisina häiriöpiikkeinä, 0‒100 °C syklauksen aikana. Syklauksen edetessä vasteen huononeminen havaitaan myöhemmin koko mittausalueella. Puolikokeellista elinikäennustemallia tarkasteltaessa havaittiin, että PCSB-liitosten lämpötila-alueesta riippuvia korjauskertoimia kuvasivat logaritmisen riippuvuuden sijaan parhaiten toisen asteen polynomifunktiot. PCSB BGA ‒rakenteille saadun ennusteen ja toteutuneen eliniän välinen ero oli pienimmillään alle 0.5 %.

Linear colliders are an option for lepton collision at several TeV. The Compact Linear Collider (CLIC) aims at electron and positron collisions at a centre of mass energy of 3 TeV. In CLIC, the main accelerating structures are designed to operate at an X-band frequency of 12 GHz with an accelerating gradient of 100 MV/m. Two significant issues in linear accelerators that can prevent high gradient being achieved are electrical breakdown and wakefields. The baseline design for the CLIC main linacs relies on a small aperture size to reduce the breakdown probability and a strong damping scheme to suppress the wakefields. The strong damping scheme may have a higher possibility of electrical breakdown. In this thesis an alternative design for the main accelerating structures of CLIC is studied and various aspects of this design are discussed. This design is known as a Damped and Detuned Structure (DDS) which relies on moderate damping and strong detuning of the higher order modes (HOMs). The broad idea of DDS is based upon the Next Linear Collider (NLC) design. The advantages of this design are: well damped wakefields, minimised rf breakdown probability and reduced size of the structure compared to the strong damping design. Procedures necessary to minimise the rf monopole fields and enhance the wakefield suppression are discussed. The rf as well as mechanical designs of a test structure are presented. This unique design forms the basis of this research and allows both the electrical breakdown and beam dynamics constraints to be simultaneously satisfied.

Free space optics (FSO) technology is proving to be an exceptionally beneficial supplement to conventional Fiber Optics and radio frequency (RF) links. FSO and RF links are greatly affected by atmospheric conditions. Hybrid FSO/RF systems have emerged as a promising solution for high data rate wireless communication. FSO technology can be used effectively in multi-user scenarios to support Point-to-Multi-Point (P2MP) networks. In this work we present and analyse a P2MP Hybrid FSO/RF network that uses a number of FSO links for data transmission from the central node to different remote nodes of the network. A common backup RF link is used by the central node to transmit data to any of the remote nodes in case of failure of any FSO links. Each remote node is assigned a transmit buffer at the central node for the downlink transmission. We deploy a non-equal priority protocol and p-persistent strategy for nodes accessing the RF link and consider the back up RF transmission link with lower frame transmission rates as compared to the FSO link. Under different atmospheric conditions, we also study various performance metrics of the network. We study the throughput from the central node to the remote nodes individually as well as the following: the average transmit buffer size, the frame queuing delay in the transmit buffers, the efficiency of the queuing systems and the frame loss probability. / Graduate

Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/fail. / This work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC.

This thesis, entitled Wireless Sensor Networks in Hostile RF Environments, was submitted to the The University of Manchester by Mr Dominic James Patrick Crutchley on 30th April 2012 for the degree Doctor of Philosophy (PhD). This thesis considers two different but related aspects of wireless communication in Wireless Sensor Networks (WSNs) operating in hostile environments. Using grain as an example of a hostile environment, the influence of hostile, attenuating media on Radio Frequency (RF) communications was considered. Further to this the implications of a hostile environment for protocol stacks were considered, and a cross-layer, cross-application framework was proposed to help future protocol designers address these issues. To achieve both these aims, the software for a bespoke WSN node was designed and implemented. The node was characterised to ensure a good understanding of its RF behaviour and practical experiments were then conducted in a small-scale grain silo to gain an understanding of attenuation and data communications within grain. Finally, a real world implementation of the proposed cross-layer, cross-application framework was produced and a small example cross-layer protocol was demonstrated running on the WSN node. It was shown that a WSN can be used to characterise communications within a hostile medium and also that data communications are achievable within grain. It was also shown that a small cross-layer, cross-application framework could ease the development of cross-layered protocols in WSN software.