Cette thèse présente le développement d'une électronique de lecture et de traitement des signaux d'un calorimètre hadronique semi

Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area occupied by the large loop filter capacitor and resistor in a low bandwidth PLL design makes the realization of traditional charge-pump PLL architecture impractical on a single die, mandating external components on the board. In order to maintain low loop bandwidth the designer is often forced to choose very low values of charge pump current which can lead to reliability issues. In this work, a semi-digital architecture for very low bandwidth monolithic PLLs is proposed. This architecture eliminates large components in traditional charge-pump PLL, thus allowing the realization of on-chip low bandwidth PLLs. A 2x2mm PLL is realized in 180nm CMOS with 75mHz bandwidth consuming 400μW power from 1.8V supply. The prototype PLL locks to an input clock of 1Hz and generates 20kHz output clock with a measured peak-to-peak jitter of 100ns. / Graduation date: 2013

The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses $N$ storage cells. The $N$ storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100~MHz to 1~GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

In a conventional charge-pump based PLL design, the loop parameters such as the band-width, jitter performance, charge-pump current, pull-in range among others govern the ar-chitecture and implementation details of the PLL. Different loop parameter specificationschange with a change in the reference frequency and inmost cases, requires careful re-designof some of the PLL blocks. This thesis describes the implementation of a semi-digital PLLfor high bandwidth applications, which is self-compensated, low-power and exhibits band-width tracking for all reference frequencies between 40 MHz and 1.6 GHz in 65nm CMOStechnology.This design can be used for a wide range of reference frequencies without redesigning anyblock. The bandwidth can be fixed to some fraction of the reference frequency during designtime. In this thesis, the PLL is designed to make the bandwidth track 5% of the referencefrequency. Since this PLL is self-compensated, the PLL performance and the bandwidthremains same over PVT corners.

Le futur collisionneur électron-positon ILC est un projet d'envergure internationale. Il doit poursuivre le programme scientifique actuellement en cours auprès du Large Hadron Collider (LHC) lorsque celui-ci aura atteint les limites de sa sensibilité. Cet ambitieux projet d'accélérateur nécessitera également la mise en place de nouveaux concepts du point de vue de la détection. Afin d'optimiser la reconstruction des événements, une approche basée sur le suivit de particule (Particle Flow) a ainsi été adoptée. Jusqu'à aujourd'hui, les calorimètres hadroniques ont souvent représenté le point faible des expériences de physique des hautes énergies auprès de collisionneurs. En effet, leur faible granularité dégrade fortement la résolution en énergie des jets reconstruits. Dans le cas de l'ILC, il est envisagé d'utiliser des calorimètres de forte granularité de manière à distinguer clairement chaque dépôt d'énergie. Il est ainsi possible d'améliorer la résolution en énergie globale de l'expérience en utilisant le détecteur le plus approprié pour caractériser chaque particule fille issue de la collision. Les membres de la collaboration CALICE sont en charge du développement de ces calorimètres ultra granulaires. Dans ce cadre, plusieurs projets de calorimètres sont à l'étude afin de s'assurer que la technologie finalement choisie soit optimale. Durant ces trois dernières années, j'ai participé au développement de l'un de ces détecteurs : le calorimètre hadronique semi digital SDHCAL. Cet instrument utilise des chambres à plaques résistives de verre (GRPC) en tant qu'élément sensible. Ce calorimètre à échantillonnage comporte 48 plans de détection successifs séparés par de l'acier. Il est segmenté latéralement en cellules de un centimètre carré, pour un total de 50 millions de canaux. La dissipation thermique de l'électronique de lecture embarquée est un facteur clef du projet. […] / The future electron-positon linear collider ILC is an international project aiming to follow and go forward the scientific program which is actually on-going at the Large Hadron Collider (LHC). Such a leptonic collider project implies also new concepts in particle detection to ensure a better event reconstruction : this can be achieved by using particle flow techniques. Until now, hadronic calorimeters are the bottleneck of particle detectors concepts. They are usually poorly granular and they contribute strongly to degrade the energy resolution of the reconstructed jets. In the ILC case, we aim to build highly granular calorimeters to distinguish each energy deposit. This way we can improve the energy resolution by using the most suitable detector to perform energy measurement for each particle. The CALICE collaboration federate the highly granular calorimeters R&D activities in order to distinguish the best technology for the final detector concept. I worked for the last three years on one of those projects : the SDHCAL, a semi digital hadronic calorimeter based on glass resistive plate chambers (GRPC). This 48 layer sampling calorimeter is segmented in cells of one square centimeter for a total of 50 millions channels. […]

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.