No description available.

In this thesis, the poly-Si TFTs with different channel width and channel length are successfully fabricated and characterized. In particular, by using the T-gate structure and body contact, we can measure the substrate current and body voltage. Therefore, short channel effects in polycrystalline silicon thin-film transistors are investigated clearly. In order to study impact ionization effect and floating body effect more carefully, we measure and compare the electrical behaviors of device with different grain boundary trap density, grain size, and channel dimension. The influences of these factors on the short channel effects are also discussed and explained. In this experiment, it is found that the devices with short channel length, exhibit improved normalized turn on current and smaller threshold voltage. But on the other hand the sever kink effect which generated by the impact ionization also observed. Moreover, the floating body under the channel region serve as a parasitic BJT as in silicon-on-insulator devices. The related single transistor latch-up is observed and discussed for short-channel devices with various channel width. The severe impact ionization effects in polycrystalline silicon thin-film transistors are investigated and characterized. By directly measuring the substrate current from conventional TFTs with body contact, the impact-ionization effects can be characterized and analyzed very clearly. An anomalous substrate current under high gate voltage is observed. The parasitic tunneling effect between inversion region and body region is proposed to explain this phenomenon. Finally, a physically-based model is established and compared with the measured substrate current. Good agreements are found when the vertical field scattering effect is included into the maximum electric field impact ionization model.

In this paper, we propose a high-yield self-aligned process to form a silicon-on-insulator MOSFET with block oxide for 1T DRAM use. The new process can overcome the problem of the previous one [1], which cannot be used for a thin BOX devices. Based on the TCAD 10.0 simulation, we compared the conventional 1T-DRAM (PDSOI) with the partially depleted SOI with block oxide ¡]bPDSOI¡^ which used the new process presented in this thesis, We find that the device with block oxide embedded on body is not only obtain good short-channel effects immunity but also reduce leakage of the P-N junction between source/drain and the body and increase the gate controlability on the channel region. Moreover, it can decrease power consumption and raise the operation speed of the 1T-DRAM. Compare to the PDSOI DRAM to carry out 10 £gA programming window, the power consumption of the new 1T-DRAM is diminished 39% of write ¡§1¡¨ and 25% of write ¡§0¡¨. Furthermore, the energy consumption during memory operation is only 23% compared to that of the conventional PDSOI DRAM and it can short the operation time but achieve a long retention time.

The objective of this research is to comprehensively compare bulk accumulation and inversion MOSFETs, and find application areas where each is superior.Short channel effect (SCE) models for accumulation and inversion MOSFETs are derived that accurately predict threshold voltage, subthreshold swing, and subthreshold current. A source/drain junction depth dependent characteristic length is derived that can be used to rapidly assess the impact of junction depth scaling on minimum channel length. A fast circuit simulation methodology is developed that uses physically based I-V models to simulate inversion and accumulation MOSFET inverter chains, and is found to be accurate over a wide range of supply voltages. The simulation methodology can be used for rapid technology optimization, and performance prediction. Design guidelines are proposed for accumulation MOSFET design; the guidelines result in a low process sensitivity, low SCE, and a subthreshold current less than the allowable limit. The relative performance advantage of accumulation/inversion MOSFETs is gate-technology dependent. In critical comparisons, on-current is evaluated by means of a full band Monte Carlo device simulation. Gate-leakage, and band-to-band tunneling leakage at the drain-substrate region are included in the performance analysis. For mid-bandgap metal gate, accumulation MOSFETs perform better than inversion MOSFETs for hi-performance (HiP) and low-operating power (LOP) applications. For tunable metal gate technology, inversion MOSFETs always perform better than accumulation MOSFETs. For dual poly technology, accumulation MOSFETs perform better than inversion MOSFETs for low standby power (LSTP) applications. A comprehensive scaling analysis has been performed on accumulation and inversion MOSFETs using both SCE models and 2-D simulations. Results show that accumulation MOSFETs can scale better than inversion MOSFETs for mid-bandgap metal gate HiP, and LOP applications; and poly gate LSTP applications.

In this paper, several new MOSFET devices, vertical MOSFET with L-shaped internal block layers (bVMOS), planar MOSFET with self-aligned internal block layers (bMOS), and Silicon-Germanium MOSFET with self-aligned internal block layers (bSGMOS) are presented. We use the sidewall spacer and etch back techniques to form the L-shaped internal block layers of bVMOS. They can suppress the short channel effects, diminish the parasitic capacitance, and reduce the leakage current cause by P-N junction between source/drain and body regions. They also provide a pass way to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, we use Si3N4 cap layer upon gate as a hard mask, combining self-aligned and sidewall spacer techniques to fabricate the internal block layers under the both sides of channel end to form bMOS. The depleted region between source/drain and body is shielded and so the short channel effects and the controllability of gate to channel are improved. The internal block layers not only maintain the character of internal block layers but also ameliorate the drawback of bVMOS. The ISE TCAD simulation results show the short channel effect is suppressed and the thermal instability is improved by the internal block layers effectively in each device. Furthermore, we employ the epitaxial silicon-germanium thin film process (bSGMOS) to form silicon-germanium thin film at source/drain region to improve the device current drive by the strain thereby enhancing the device performance.

This paper investigates the device behavior of a novel pseudo tri-gate ultrathin channel vertical MOSFET with source/drain tie (S/D tie), the PTG-SDT VMOS. The S/D tie (SDT) of this novel device circumvents short channel effect (SCEs). A double- surround-gate (the mid-gate and the spacer gate) is also presented to investigate the effect of S/D tie. According to the 2D simulation, three kinds of pseudo vertical MOSFETs are now proposed. The first one is to investigate the device characteristics of the new PTG-SDT VMOS. Our proposed structure also mitigates self-heating effect (SHEs), thereby enhancing the drain drive current and the thermal stability. Owing to its ultrathin channel (Tsi = 10 nm), the PTG-SDT VMOS has a very low subthreshold swing of 60 mV/dec, for channel lengths from 90 nm down to 40 nm. It is also found to control drain-induced barrier lowing (DIBL) and to have an excellent Gm of 4.5 mS/£gm at the channel length 40 nm. The second one, we proposed the ultrathin channel pseudo tri-gate vertical MOSFET with natural source/drain tie (NSDT), the big source/drain tie (BSDT), the SDT and the without source/drain tie (WSDT) VMOS. The PTG VMOS of this novel structure circumvents short channel effects (SCEs). A new natural S/D tie (N-SDT) is also presented to investigate of the PTG VMOS. According to 2D simulation, the PTG-NSDT also show the excellent thermal dissipated such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 47% and 66% respectively, thereby enhancing the ON-state and OFF-state current ratio. In addition, the dependence of GIDL current on body bias and temperature is characterized and discussed when the source and drain interchanged. Although the PTG VMOS keep the double-surround-gate and S/D tie structure, the design flow is more simplify even increase the drain drive current and immunity the SHEs.

I propose compact models of single-gate (SG) and double-gate (DG) JFETs predicting the current-voltage characteristics for both long and short channel devices. In order to make the current equation continuous through all operating conditions from subthreshold to well-above threshold, without non-physical fitting parameters, mobile carriers in depletion region are considered. For describing the short channel behavior, relevant parameters extracted from the two-dimensional analytical solution of Poisson's equation are used for modifying long channel equations. Comparisons of models with the numerical simulation showing close agreement are presented. Based on models, merits of DG JFET over SG JFET and SG MOSFET are discussed by examining the schematic circuit diagram describing the relation between gate and channel potentials for each device. / text

The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). <br /><br /> A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 &mu;m, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. <br /><br /> An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion.

The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). <br /><br /> A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 &mu;m, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. <br /><br /> An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion.

In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical MOSFET (JVMOS). Also, we examine the advantages of the double-gate structure and the short-channel behavior of the junctionless transistors. According to the 2D simulation studies, the proposed JLVMOS can achieve better short-channel characteristics (JLVMOS: 62.04 mV/dec S.S., 23.96 mV/V DIBL; JLPMOS: 77.67 mV/dec S.S., 146.07 mV/V DIBL) as compared with the planar transistor, chiefly owing to the double-gate scheme. This proves that only the double-gate device has better gate controllability over the channel region to reduce the short-channel effect. More importantly is that the JLVMOS has a bulk Si starting material, in which the SOI-induced self-heating effects and the fabrication cost can be well suppressed and reduced, respectively. In comparison with the JVMOS, our proposed JLVMOS exhibits better S.S. and reduced DIBL. Furthermore, although the analog/RF properties of the JLVMOS are somewhat degraded, due to its simple fabrication process, our proposed JLVMOS can become one of the mainstream technology for future CMOS applications.