In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using these circuit simulators and compared their outputs. The simulators are evaluated using design metrics in order to quantify their performance and identify efficient circuit simulators. In addition, I designed a sigma-delta modulator and its individual components using the analog behavioral language Verilog-A. Initially, I performed simulations of individual components of the sigma-delta modulator and later of the whole system. Finally, CMOS (complementary metal-oxide semiconductor) transistor-level circuits were designed for the differential amplifier, operational amplifier and comparator of the modulator.

Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.

Cette thèse présente un émetteur radio-fréquences, composé d’un synthétiseur numérique de fréquences, lui-même construit autour d’un sigma delta et d’un interpolateur de phase, ainsi que d’un oscillateur verrouillé par injection. Le synthétiseur numérique direct génère des fréquences de 400 à 500 MHz avec une résolution fréquentielle d’au moins 60 Hz. L’oscillateur verrouillé par injection, quand à lui, transpose ces fréquences dans la bande Bluetooth en assurant une multiplication de fréquences par 5. De plus, l’oscillateur verrouillé filtre le bruit de phase du signal d’injection jusqu’à récupérer celui de l’oscillateur libre. La bande passante de l’oscillateur verrouillé par injection peut être programmée numériquement. Cet émetteur a été développée dans une technologie CMOS 65 nm. / This Ph.D dissertation presents a radio-frequency transmitter, made of a direct digital frequency synthesizer, built around a sigma delta and a phase interpolator, and an injection locked oscillator. The direct digital synthesizer generates frequencies between 400 and 500 MHz with a frequency resolution better than 60 Hz. On the other hand, the injection locked oscillator up-converts synthesizer output up to the Bluetooth band by multiplying frequencies by 5. Moreover, the locked oscillator filters injected signal phase noise up to recover the one of the free running oscillator. The locked oscillator bandwidth can be tuned digitally. This transmitter has been developed on 65-nm CMOS technology.

La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz. / Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz.

Research Doctorate - Doctor of Philosophy (PhD) / This thesis presents results on optimal coding and decoding of discrete-time stochastic signals, in the sense of minimizing a distortion metric subject to a constraint on the bit-rate and on the signal transfer function from source to reconstruction. The first (preliminary) contribution of this thesis is the introduction of new distortion metric that extends the mean squared error (MSE) criterion. We give this extension the name Weighted-Correlation MSE (WCMSE), and use it as the distortion metric throughout the thesis. The WCMSE is a weighted sum of two components of the MSE: the variance of the error component uncorrelated to the source, on the one hand, and the remainder of the MSE, on the other. The WCMSE can take account of signal transfer function constraints by assigning a larger weight to deviations from a target signal transfer function than to source-uncorrelated distortion. Within this framework, the second contribution is the solution of a family of feedback quantizer design problems for wide sense stationary sources using an additive noise model for quantization errors. These associated problems consist of finding the frequency response of the filters deployed around a scalar quantizer that minimize the WCMSE for a fixed quantizer signal-to-(granular)-noise ratio (SNR). This general structure, which incorporates pre-, post-, and feedback filters, includes as special cases well known source coding schemes such as pulse coded modulation (PCM), Differential Pulse-Coded Modulation (DPCM), Sigma Delta converters, and noise-shaping coders. The optimal frequency response of each of the filters in this architecture is found for each possible subset of the remaining filters being given and fixed. These results are then applied to oversampled feedback quantization. In particular, it is shown that, within the linear model used, and for a fixed quantizer SNR, the MSE decays exponentially with oversampling ratio, provided optimal filters are used at each oversampling ratio. If a subtractively dithered quantizer is utilized, then the noise model is exact, and the SNR constraint can be directly related to the bit-rate if entropy coding is used, regardless of the number of quantization levels. On the other hand, in the case of fixed-rate quantization, the SNR is related to the number of quantization levels, and hence to the bit-rate, when overload errors are negligible. It is shown that, for sources with unbounded support, the latter condition is violated for sufficiently large oversampling ratios. By deriving an upper bound on the contribution of overload errors to the total WCMSE, a lower bound for the decay rate of the WCMSE as a function of the oversampling ratio is found for fixed-rate quantization of sources with finite or infinite support. The third main contribution of the thesis is the introduction of the rate-distortion function (RDF) when WCMSE is the distortion metric, denoted by WCMSE-RDF. We provide a complete characterization for Gaussian sources. The resulting WCMSE-RDF yields, as special cases, Shannon's RDF, as well as the recently introduced RDF for source-uncorrelated distortions (RDF-SUD). For cases where only source-uncorrelated distortion is allowed, the RDF-SUD is extended to include the possibility of linear-time invariant feedback between reconstructed signal and coder input. It is also shown that feedback quantization schemes can achieve a bit-rate only 0.254 bits/sample above this RDF by using the same filters that minimize the reconstruction MSE for a quantizer-SNR constraint. The fourth main contribution of this thesis is to provide a set of conditions under which knowledge of a realization of the RDF can be used directly to solve encoder-decoder design optimization problems. This result has direct implications in the design of subband coders with feedback, as well as in the design of encoder-decoder pairs for applications such as networked control. As the fifth main contribution of this thesis, the RDF-SUD is utilized to show that, for Gaussian sta-tionary sources with memory and MSE distortion criterion, an upper bound on the information-theoretic causal RDF can be obtained by means of an iterative numerical procedure, at all rates. This bound is tighter than 0:5 bits/sample. Moreover, if there exists a realization of the causal RDF in which the re-construction error is jointly stationary with the source, then the bound obtained coincides with the causal RDF. The iterative procedure proposed here to obtain Ritc(D) also yields a characterization of the filters in a scalar feedback quantizer having an operational rate that exceeds the bound by less than 0:254 bits/sample. This constitutes an upper bound on the optimal performance theoretically attainable by any causal source coder for stationary Gaussian sources under the MSE distortion criterion.

Les convertisseurs analogiques-numériques fondés sur le principe de la modulation §¢ sont capables de fonctionner à des résolutions très élevés. L'utilisation en interne d'un CAN et d'un CNA multibit permet de réduire le taux de suréchantillonnage, les contraintes imposées par les circuits actifs, amé- liore la stabilité de la boucle du modulateur, mais rend celui-ci très sensible aux imperfections des composants du convertisseur numérique analogique (CNA) interne situé dans le chemin de retour. Les erreurs statiques dues aux non idéalités des circuits constitutifs de ce CNA peuvent être corrigées au moyen de techniques d'appariement dynamique des composants (DEM). Ce travail de thèse est consacré entre autre à l'étude théorique de ces techniques de correction des défauts des cellules des CNA multibits. Après avoir rappelé le principe de la conversion §¢ d'une part, et les différentes sources d'erreurs dominantes dans le cas multibit d'autre part, les techniques d'appariement existantes sont analysées et comparées. Nous soulignons les avantages, les inconvénients, et les domaines d'applications préférentiels de chacune. Le coeur du travail consiste en la proposition de quatre nouvelles techniques d'appariement dynamique. Les deux premières dérivent de la méthode de la moyenne des données (DWA), l'une pour le cas passe-bas du premier ordre, l'autre dans le cas passe-bande du second ordre. Les deux dernières propositions (appelées MDEM et STDEM) dérivent des deux algorithmes de tri (SDEM) et d'arborescence (TDEM) : elles conviennent à une mise en forme des erreurs d'ordre élevé et sont destinées aux applications passe-bas et passe-bande de haute performance. Ces quatre méthodes proposées ont été mises en équation et leurs performances confirmées par diverses simulations. Une implantation des algorithmes MDEM et STDEM a été faite au niveau cellule standard jusqu'à l'étape finale de routage en technologie CMOS 0.35 ¹m. L'ensemble des résultats des simulations au niveau système et au niveau transistor conforme l'avantage des techniques développées dans ce travail en termes de surface occupée et aussi de fréquence maximale d'application, si on les compare avec les algorithmes conventionnels de SDEM. Dans une dernière partie, les erreurs dynamiques du CNA, en particulier l'effet de la gigue d'horloge, le glitch, la dissymétrie des temps de transition, l'injection de charge (CFT) et la métastabilité du quantificateur sont également analysés. A l'issue de ces réflexions, une nouvelle cellule de CNA incluant un bloc limitant la plage dynamique de la commande d'entrée (SRD) est proposée. Elle possède une structure de remise à zéro partielle (semi-RZ) qui permet de bénéficier à la fois de l'avantage de la cellule RZ et non RZ. De plus, l'effet du retard du bloc de DEM est compensé par une modification dans l'architecture convenant aux applications passe-bande haute fréquence.

The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.

With the developing radar technology, radars have been started to be used in the airborne platforms due to the need of fast, accurate and reliable information about the enemies. The most important and tactically needed information is the movements in an observation area. The detection of a ground moving target buried in a dense clutter environment from a moving air platform is a very challenging problem even today. The geometry of the operation, the course of the flight and structure of the clutter are the most effective parameters of this problem. There are some &ldquo / Ground Moving Target Indication&rdquo / (GMTI) techniques that have been studied for the last twenty years to overcome this problem. In this thesis, the simulation of some of these techniques in a realistic environment and the comparison of their performances are discussed. In this work, a GMTI simulator is developed to generate the environment containing the clutter and the noise signals, to locate and simulate the targets in this environment and to apply the GMTI techniques on the raw data generated by the simulator. The generation of the clutter signals including the internal clutter motion (ICM) for different types of clutter distributions is one of the most important parts of this thesis. The GMTI techniques being investigated throughout this thesis are &ldquo / Displaced Phase Center Antenna&rdquo / (DPCA), &ldquo / Along-Track Interferometry&rdquo / (ATI), &ldquo / Adaptive DPCA&rdquo / , &ldquo / Pre-Doppler Sigma-Delta STAP&rdquo / and &ldquo / Post-Doppler Sigma-Delta STAP&rdquo / techniques. These techniques are compared according to their clutter suppression and target detection performances under different environmental conditions.

The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.

La logique supraconductrice RSFQ (Rapide Single Flux Quantum) est une solution très attractive pour le <br />traitement des données à très haute fréquence avec une dissipation très faible et des performances nettement <br />supérieures à ce que la technologie CMOS pourra offrir dans la prochaine décennie. La technologie RSFQ <br />en nitrure de niobium (NbN) en cours de développement au CEA-G est basée sur des jonctions Josephson <br />NbN/Ta_{X}N/NbN auto-shuntées qui présentent une fréquence d'oscillation maximum proche du THz jusqu'à <br />10 K. L'objectif de cette recherche a été d'appliquer cette technologie NbN 9K à un CAN (Convertisseur <br />Analogique-Numérique) adaptable aux télécommunications spatiales. Une architecture de type CAN <br />sigma-delta a été étudiée, sur-échantillonnant à 200 GHz de fréquence d'horloge un <br />signal avec une bande de 500 MHz et modulé sur une porteuse de 30 GHz. En particulier une horloge, <br />un comparateur et différents portes <br />logiques ont été étudiés et conçus pour opérer à 200 GHz ainsi qu'un modulateur sigma-delta passe-bande <br />du troisième ordre dont les performances SNR, SFDR, devraient après optimisation satisfaire les objectifs <br />visés. La complexité de l'architecture du filtre de décimation a été analysée. Certains composants de base <br />du filtre, des diviseurs de fréquence et des registres à décalage, ont été étudiés et dessinés, enfin quelques <br />méthodes de test du modulateur sont proposées. Le travail d'implémentation de circuits NbN en technologie <br />multi-niveaux a été traité conduisant à la réalisation complète de deux lots de circuits qui pour des raisons <br />technologiques clarifiées ensuite n'ont pu aboutir au test des portes logique du CAN. Cependant, les marges de <br />fonctionnement des portes logiques NbN ont été déterminées grâce à la caractérisation de jonctions, SQUIDs <br />et de filtres (résonateurs) micro-ondes. Finalement, une étude comparative entre des circuits à jonctions NbN <br />auto-shuntées opérant à 9K en réfrigération allégée et des circuits similaires obtenus en fonderie Nb basés sur <br />des jonctions Nb/AlO_{X}/Nb shuntées en externe opérant à 4K, démontre tous les avantages qu'on peut espérer <br />attendre de la technologie NbN.