The main goal of this thesis is to study the saturation problem arisen from the integrator in a sigma- delta analog- to- digital modulator , especially when the order of the circuit is higher than two .Signal passes through each stage of integrators yield saturation problem. This situation will miss some part of messages .Unable to deliver datas accurately to next stage of the integrator , the output digital signals will be incorrect and can't be recovered to original analog signals . Hence, this thesis proposes an anti-wind-up method by taking sliding mode control theory to avoid integrator saturation. After that, we are going to design and implement two third order sigma-delta modulators based on this method. Simulation and experiment results show the validity of the method and the significant improvement of avoiding saturation problem, and guarantee the designed circuits can translate signals to terminal accurately .

<p>This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.</p><p>The comparator is designed for time-interleaved bandpass sigma-delta ADC.</p><p>Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.</p><p>The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.</p>

Biosensors are extremely powerful analytical tools instrumental for detection and quantification of bio-molecules such as DNA, peptides and even metabolites. The recent decade has seen a surge in biosensing applications ranging from molecular diagnostics, environmental monitoring, basic life science research, forensics and biothreat monitoring. The existing biosensor systems of today, however, have several limitations. They are expensive, bulky in size, power hungry, hard to use and with access limited to core facilities. Among other disadvantages, these impediments discourage the availability of point-of-care testing and low cost in-vitro diagnostics (IVD) in locations such as developing and third world countries. The main bottleneck in the development of low-cost and compact biosensors is the effective and efficient integration of several complex components present inside a typical biosensor. These components are the sample preparation, biomolecular recognition, signal transduction and data analysis. With vii the recent advancements in very large scale integration (VLSI) and fabrication technologies, it is now possible to integrate several of these biosensing components into a small form factor. This thesis proposes leveraging the utilization of VLSI technology to develop a low-cost, miniature, portable, fast analysis, high throughput and low power consumption biosensor solution. Apart from the miniaturization bene- fits, employing VLSI technology facilitates low-cost, high yield and low process variation. We present complementary metal-oxide semiconductor (CMOS) integrated microsystem solutions for fluorescence, bioluminescence and electrochemical biosensing. Simulation models are provided for the microsystems and the specifications for the constituent components derived. A common problem in the transducer development of biosensors that we specifically focus on, is the presence of a large non-informative signal called the background signal. This background signal can be several orders of magnitudes higher than the signal of interest and it reduces the overall sensitivity of the biosensor. Existing transducer solutions rely on very high dynamic range, expensive and power hungry solutions to solve the problem of high background signal. To address the problem of overwhelming background signal, this thesis proposes an active background subtraction architecture merged with a Σ∆ modulator. The robust, versatile architecture can be conveniently employed for optical and electrochemical sensing. The proposed architecture attenuates the background signal very early in the signal chain, achieving high dyviii namic range while significantly relaxing the performance requirements of the subsequent circuit blocks in terms of power dissipation, area and bandwidth requirements. To validate the proposed solution, two CMOS IC prototypes were developed for optical and electrochemical sensing respectively. A 12 × 12 array of Σ∆ photodetector with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. The pixel performance has been validated with over 140dB dynamic range and the ability of subtract the background subtraction current validated from 10nA to 10fA. Real time pyrosequencing experiment has also been performed utilizing the photodetector array. A 12 × 12 array of Σ∆ electrochemical sensor with in-pixel background subtraction was developed in 0.18µm standard CMOS technology. Capacitive charge redistribution circuit architecture for bipolar current measurements was employed. The circuit performance was validated over the wide input current range of 100nA to 1pA. / text

In this thesis, a time-based oversampling sigma-delta analog-to-digital converter (ADC) architecture is introduced. This system uses time, instead of voltage, as the analog variable for it quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital pulse. The sigma-delta loop integrator, comparator, and subtractor are all time-based circuits and implemented by using only digital gates. The only voltage-based circuit is voltage-to-time Converter (VTC) which requires only a current source. No amplifier is required in the entire circuit. As a proof of concept, the simulation results for a prototype ADC incorporating this time-based sigma-delta ADC architecture is presented. / text

This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V. The comparator is designed for time-interleaved bandpass sigma-delta ADC. Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed. The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.

Techn. University, Diss., 2004--Darmstadt.

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Submitted by Igor Miranda (engigordantas@gmail.com) on 2018-01-12T19:20:36Z No. of bitstreams: 1 Tese - Igor Miranda - Versão Final com Capa.pdf: 4371607 bytes, checksum: 8044fe0ec518f4129d73e83eb19e44ba (MD5) / Approved for entry into archive by Vanessa Reis (vanessa.jamile@ufba.br) on 2018-01-15T15:26:30Z (GMT) No. of bitstreams: 1 Tese - Igor Miranda - Versão Final com Capa.pdf: 4371607 bytes, checksum: 8044fe0ec518f4129d73e83eb19e44ba (MD5) / Made available in DSpace on 2018-01-15T15:26:30Z (GMT). No. of bitstreams: 1 Tese - Igor Miranda - Versão Final com Capa.pdf: 4371607 bytes, checksum: 8044fe0ec518f4129d73e83eb19e44ba (MD5) / Os sistemas de detecção de disparos de arma de fogo baseados em monitoramento acústico têm se mostrado ferramentas eficazes no combate à violência urbana. Entretanto, as soluções disponíveis no mercado têm apresentado custos elevados, tornando a tecnologia pouco acessível. Reduzir o custo de implementação dos numerosos sensores acústicos presentes nesse tipo de sistema pode representar uma redução do custo global. As principais funcionalidades de um sensor acústico são a detecção de explosões e a estimação a direção de chegada da frente de onda, que são implementadas por meio de diversas operações de Processamento Digital de Sinais (PDS). Uma estratégia que tem sido utilizada em sistemas similares, como na área de ultrassom, para redução da complexidade dos algoritmos é o processamento de sequências binárias provenientes de conversores Analógico/Digital (A/D) sigma-delta sem realizar a demodulação. Essa abordagem, apesar de vantajosa, ainda não foi devidamente explorada na literatura científica para aplicações de acústica e detecção de tiros. Este trabalho teve como objetivo explorar e desenvolver técnicas de PDS para otimizar a utilização de conversores A/D sigma-delta em sistemas de detecção de disparos de arma de fogo, visando reduzir o custo desses sistemas em comparação aos convencionais através da diminuição da complexidade das operações. Métodos de propósito gerais para o processamento de sequências sigma-delta foram introduzidos, dentre eles estão um algoritmo para detecção de sinais impulsivos e dois algoritmos para o cálculo eficiente da transformada discreta de Fourier. Com base nesses algoritmos, foram desenvolvidas técnicas para explorar a diversidade espacial de dois microfones na detecção de explosões e na estimação da direção de chegada. Todos os algoritmos e métodos desenvolvidos foram validados através de simulações ou experimentos com dados de disparos de arma de fogo reais, apresentando resultados satisfatórios.

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.