Design Space Exploration (DSE) is the exploration of a space of possible designs with the goal of finding some optimal design according to some constraints and criteria. Within embedded systems design, automated DSE in particular can allow the system designer to efficiently find good solutions in highly complex design spaces. One particular tool for performing automated DSE is IDeSyDe which uses Constraint Programming (CP) and constraint optimization for modelling and optimization. The constraint models of DSE often include some real-valued parameters, but optimized CP-solvers typically require integer arguments. This makes it necessary to discretize the problem in order to make the approach useful in practice, effectively limiting the size of the search space significantly. The effects of this discretization procedure on the quality of the solutions have not previously been well studied. An investigation into how this kind of discretization affects the approximate solutions could make the approach more rigorous, and possibly also uncover exploitable details that could facilitate the development of even more efficient algorithms. This project presents a convergence proof based in CP and Multiresolutional analysis (MRA), including a practically useful error bound for solutions obtained with different discretizations. In particular, the mapping and scheduling of Syncronous Data Flow (SDF) models for streaming applications onto tile-based multiple processor system-on-chip platforms with a common time-division multiplexing bus interconnect is studied. The theoretical results are also verified using IDeSyDe for a few different configurations of applications and platforms. It can be seen that the experiments behave as predicted, with first order convergence in total error and adherence to the bound. / Designrymdsutforskning är benämningen för en systematisk utforskning av en rymd av möjliga designer i syfte att hitta bra eller optimala lösningar som optimerar något mål och som uppfyller krav och begränsningar. Automatiserad designrymdsutforskning har i synnerhet sett utveckling för tillämpningar inom design av inbyggda system, där den ständigt ökande komplexiteten hos moderna plattformar motiverat utvecklingen av nya metoder. Två stora delar är nödvändiga för att kunna tillämpa designrymdsutforskning för design av inbyggda system: en modell av systemet och en optimiseringsprocess. Beroende på situation kan systemmodeller variera från detaljerade simuleringar på transistornivå till övergripande analytiska modeller på applikationsnivå eller högre. Detaljerade simuleringar gör det möjligt att utvärdera en viss lösning mycket noggrant, men till en hög beräkningskostnad. Med analytiska modeller är det istället billigt att utvärdera enskilda lösningar, men på bekostnad av noggrannhet. På samma sätt kan olika optimeringsprocesser också användas: snabbare approximativa algoritmer kan användas för att hitta lösningar relativt snabbt men utan garantier för optimalitet, medans mer uttömmande algoritmer typiskt kräver mycket beräkningskraft. Ett verktyg för automatiserad designrymdsutforskning är IDeSyDe. IDeSyDe använder villkorsbaserade modeller och uttömmande sökning genom Branch and Bound. Optimerade algoritmiska lösare för villkorsprogrammeringsproblem kräver ofta heltalsparametrar. Modeller för designrymdsutforskning innehåller å andra sidan ofta kontinuerliga parametrar. På grund av detta är det ofta nödvändigt att disktretisera problemet för att effektivt kunna hitta lösningar. Eftersom en diskretisering begränsar mängden lösningar i sökrymden riskerar en sådan omformulering att ta bort även optimala lösningar. En designrymdsutforskningsalgoritm som utnyttjar diskretisering av designrymden måste på grund av detta generellt ses som en approximativ algoritm. Hur en sådan diskretisering påverkar lösningarna -- dvs. hur nära de approximativa lösningarna kan förväntas komma den optimala lösningen utan diskretisering -- har dock inte studerats i närmare detalj. En bättre förståelse för hur diskreta, approximativa problem och lösningar relaterar till sina exakta motsvarigheter kan ge metoden mer rigör. En undersökning av den underliggande matematiken har också potential att belysa andra samband och strukturer som potentiellt skulle kunna användas för att utveckla bättre eller mer effektiva algoritmer. I den här rapporten presenteras ett konvergensbevis baserat på villkorsprogrammering och multiupplösningsanalys med ett begränsat felintervall i termer av probleminstansspecifika parametrar och en diskretiseringsparameter. Beviset är framtaget för tillämpning med IDeSyDe och är därför begränsat till en kombination av modeller som verktyget för närvarande stödjer, nämligen strömmande-dataflödesapplikationer beskrivna som synkrona dataflödesmodeller (Synchronous Data Flow, SDF) samt en ''tile''-baserad modell för system med flera processorer på ett chip (MPSoC) med en gemensam tidspartitionerad multiplexor-bus för kommunikation mellan processor-''tiles''. De teoretiska resultaten är verifierade och tillämpade på ett flertal exempelfall beräknade med IDeSyDe, där konvergensen studerats experimentellt.

Analysis was done to determine fuel optimal translunar trajectories from Earth geostationary transfer orbit to a specified target lunar orbit for a small satellite navigation and communication mission. The study included the optimization of impulsive and finite burn transfers. The inclusion of finite burns was necessary due to the low thrust nature of a small satellite propulsion system. Finite burn optimization was achieved using suboptimal parameterization control theory. The orbital parameters of the initial Earth orbit as well as the target lunar orbit were varied to see how this affected the optimal transfer results. Additionally, two engine thrust levels were explored to find the impact on the fuel mass required. All optimization analyses were completed using Copernicus, a trajectory optimization software package developed at the University of Texas at Austin for the National Aeronautics and Space Administration (NASA).

No description available.

As commercial lunar rovers are being developed and planned to fly from next year, in the context of a global momentum for lunar exploration, the mindset of system design is shifting to a product-oriented approach (as opposed to traditionally single mission-designed system). This deeply affects the system engineering discipline, which is also evolving through the development of more integrated, model-centric methodologies such as Model-Based System Engineering (MBSE). This Master Thesis combines 2 research questions:- How to adapt systems engineering processes and tools to a commercially-driven / product-oriented approach?- How to leverage new developments (e.g MBSE) within the system engineering discipline to support the rover design transition to a product-oriented philosophy? These research questions are investigated through this Master Thesis, carried out as a 6-month internship at ispace Europe (Luxembourg), a global lunar exploration company developing landers, rovers and data tools. The Master Thesis is applied to ispace’s Exploration Rover currently under development within the Polar Ice Explorer (PIE) mission with support from the Luxembourg Government.The goal of this Master Thesis is to develop an integrated toolchain (set of tools) for efficiently designing rover products (Exploration Rover), including platform configuration for a given mission concept and set of payloads, system sizing and mission analysis. The chosen methodology can be summarized as:1. Adapting PIE models to a generic, parametric/configurable toolset that can be used for mission/platform analysis and optimization2. Defining the Exploration Rover toolchain requirements & architecture, and selecting its environment (trade-off including MBSE solutions)3. Building the Exploration Rover toolchain, integrating models inside the defined architecture By maturing existing models, leveraging new software functionalities (in this case Valispace) and MBSE practises along with adding new parametric models for quick feasibility studies and integrating all models together, it was successfully shown that this integrated toolchain can support rover products definition, performing frequent and insightful design iterations, analysis and trade-offs. Not only does the toolchain comply with the product-approach but also successfully supports the Polar Ice Explorer (PIE) mission, by directly contributing to the system engineering activities and models of the Phase B. Therefore, the Master Thesis proved to be a successful demonstrator for developing more product-driven rovers, by leveraging new practices within the system engineering discipline. / Eftersom kommersiella månrovers utvecklas och planeras att flyga från nästa år, i samband med en global fart för månutforskning, går tankesättet för systemdesign över till produktorienterat tillvägagångssätt (i motsats till traditionellt endast uppdragsdesignat system). Detta påverkar djupt systemteknikdisciplinen, som också utvecklas genom utvecklingen av mer integrerade, modellcentrerade metoder som Model-Based System Engineering (MBSE).  Denna masteruppsats kombinerar två forskningsfrågor: - Hur anpassar man systemtekniska processer och verktyg till en kommersiellt driven / produktorienterad strategi? - Hur kan man utnyttja ny utveckling (t.ex. MBSE) inom systemteknikdisciplinen för att stödja rover-designövergången till en produktorienterad filosofi?  Dessa forskningsfrågor undersöks genom denna magisteruppsats, som genomfördes genom en praktik under 6 månader på ispace Europe (Luxemburg), ett globalt månutforskningsföretag som utvecklar landare, rovers och dataverktyg. Magisteruppsatsen tillämpas på ispaces Exploration Rover som för närvarande är under utveckling inom Polar Ice Explorer (PIE) -uppdraget, med med stöd från den luxemburgska. Målet med detta examensarbete är att utveckla en integrerad verktygskedja (uppsättning verktyg) för att effektivt utforma roverprodukter (Exploration Rover), inklusive plattformskonfiguration för ett givet uppdragskoncept och uppsättning nyttolast, systemstorlek och uppdragsanalys.  Den valda metoden kan sammanfattas som: 1. Anpassa PIE -modeller till en generisk, parametrisk / konfigurerbar verktygssats som kan användas för uppdrag / plattformsanalys och optimering 2. Definiera Exploration Rover-verktygskedjans krav och arkitektur och välja dess miljö (avvägning inklusive MBSE-lösningar) 3. Bygga Exploration Rover -verktygskedjan, integrera modeller inom den definierade arkitekturen  Genom att utveckla befintliga modeller, utnyttja nya mjukvarufunktioner (här Valispace) och MBSE -metoder tillsammans med att lägga till nya parametriska modeller för snabba genomförbarhetsstudier och integrera alla modeller tillsammans: visades det att denna inbyggda integrerade verktygskedja kan stödja rover -produktdefinition, som utför ofta och insiktsfulla design iterationer, analyser och avvägningar. Verktygskedjan följer inte bara produktmetoden utan stöder också framgångsrikt Polar Ice Explorer (PIE) -uppdraget genom att direkt bidra till systemtekniska aktiviteter och modeller i Phase B.  Därför visade masteruppsatsen sig vara en framgångsrik demonstrator för att utveckla mer produktdrivna rovers, genom att utnyttja nya metoder inom systemteknikdisciplinen.

In this thesis, the design and particularities of a unique and revolution- ary scalable propulsion system are presented. A spacecraft mechanical design is included together with a mission definition, aiming to provide a context for a technology demonstration in space of an Hybrid Rocket Motor (HRM) as satellite thruster. Rocket motors have been around for many decades, with their use mainly focused on launch vehicles and large satellites, thus restricting the access to space to institutions with big budgets. To overcome this limitation, the application of a cost-effective type of rocket motor without a heritage of space utilization is explored. This is the implementation of an HRM as satellite thruster. In Chapter 2, the characteristics of this particular case of chemical rocket motor are presented in detail. The HRM applied for the present mission is a particular case of an in- house developed motor design method. As presented in Chapter 7, a scalable and versatile mechanical and propulsion design have been elab- orated following the maturation of a scalability software (Appendix A). The combination of these constitute a valuable tool allowing for a fast and accurate motor design for the desired scenario. Taking advantage of this straightforward tool, an attractive mission was defined to provide a meaningful context for the maiden use of an HRMin space. A micro satellite deep space mission, defined in Chapter 3, was chosen to validate the tool and prove Hybrid Rocket Motors (HRMs) capabilities, showing the benefits of its use over other propulsion systems already available, specifically in the small satellite family. The spacecraft design was tackled aiming to support the motor’s scalable concept while complying with the mission requirements and space standards. The out- come is an easily adaptable satellite design, justified in Chapter 8. The performed structural simulations are outlined in Appendix C to validate the developed design. Ultimately, this thesis work intends to provide the space community with a noteworthy product, opening the access to interplanetary missions provided the reduced mission costs of small satellites mounted with anHRM as propulsion system. Arising from the thesis content, research papers (Part v) have been published and presented in distinguished congresses, contributing to space development.

Los diseños multi-núcleo se están convirtiendo en la solución más popular a la mayoría de las limitaciones de los diseños mono-núcleo. Un diseño multi-núcleo sigue el paradigma de diseño conocido como Sistema dentro del Chip (o SoC , del inglés System on-Chip), en el cuál varios núcleos se integran en un mismo chip. Las prestaciones de un diseño SoC dependen en gran medida de la infraestructura de interconexión que implemente. En este contexto, el paradigma de diseño conocido como red dentro del chip (o NoC, del inglés Network on-Chip) surge como una solución a los desafíos de interconexión presentes en los nuevos diseños de tipo SoC. Para un diseño concreto, el alto número de posibles soluciones basadas en NoCs incrementa la complejidad de analizar el espacio de diseño y de elegir la NoC óptima. La solución más común a este problema pasa por la utilización de herramientas de alto nivel para la obtención de estimaciones sobre las prestaciones de cada posible solución, que posteriormente serán utilizadas por el diseñador para cribar el espacio de diseño en las primeras etapas del proceso de diseño. Pero hay una gran diferencia entre las prestaciones estimadas por herramientas de alto nivel y las prestaciones reales obtenidas una vez el sistema se implementa. Este trabajo se centra en el desarrollo de nuevas herramientas de alto nivel de diseño, modelado y simulación de NoCs, con el fin de cribar el espacio de diseño de los candidatos menos atractivos. En un primer paso, nos centraremos en el diseño y desarrollo de una plataforma experimental para analizar arquitecturas alternativas para el diseño de NoCs de forma que permitan evaluar cualquier punto del espacio de diseño de forma rápida y precisa, mediante la anotación de algunos parámetros claves del proceso de síntesis física. En el segundo paso, se revisaron arquitecturas y técnicas de diseño adoptadas del dominio de las redes de interconexión fuera del chip, seleccionando las más prometedoras y, en algunos casos, explotando las características propias de las redes dentro de chip para obtener nuevas soluciones. Este paso, preliminar al desarrollo de la herramienta para la realización de exploraciones del espacio de diseño (o herramientas DSE, del inglés Design Space Exploration), tiene como objetivo depurar las técnicas para la abstracción de los efectos de la implementación física de las NoCs sobre sus prestaciones. / Gilabert Villamón, F. (2011). Design Space Exploration for Networks On-chip [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/11521

The phenomenal density growth in semiconductors has resulted in the availability of billions of transistors on a single die. The time-to-design is shrinking continuously due to aggressive competition. Also, the integration of many discrete components on a single chip is growing at a rapid pace. Designing such heterogeneous systems in short duration is becoming difficult with existing technology. Field-Programmable Gate Arrays offer a good alternative in both productivity and heterogeneity issues. However, there are many obstacles that need to be addressed to make them a viable option. One such obstacle is the lack of early design space exploration tools and techniques for FPGA designs. This thesis develops techniques to evaluate systematically, the available design options before the actual system implementation. The aspect which makes this problem interesting, yet complicated, is that a system-level optimization is not linearly summable. The discrete components of a system, benchmarked as best in all design parameters — speed, area and power, need not add up to the best possible system. This work addresses the problem in two ways. In the first approach, we demonstrate that by working at higher levels of abstraction, one can achieve orders of improvement in productivity. Designing a system directly from its behavioral description is an on-going effort in industry. Instead of focusing on design aspects, we use these methods to develop quick prototypes and estimate the design parameters. Design space exploration needs relative comparison among available choices and not accurate values of design parameters. It is shown that the proposed method can do an acceptable job in this regard. The second approach is about evolving statistical techniques for estimating the design parameters and then algorithmically searching the design space. Specifically, a high level power estimation model is developed for FPGA designs. While existing techniques develop power model for discrete components separately, this work evaluates the option of generic power model for multiple components. / Master of Science

Automating the generation of test cases for software is an active area of research. Specification based test generation is an approach in which a formal representation of a method is analyzed to generate valid test cases. Constraint solving and state space exploration are important aspects of the specification based test generation. One problem with specification based testing is that the size of the state space explodes when we apply this approach to a code of practical size. Hence finding ways to reduce the number of candidates to explore within the state space is important to make this approach practical in industry. Korat is a tool which generates test cases for Java programs based on predicates that validate the inputs to the method. Various ongoing researches intend to increase the tools effectiveness in handling large state space. Parallelizing Korat and minimizing the exploration of invalid candidates are the active research directions. This report surveys the basic algorithms of Korat, PKorat, and Fast Korat. PKorat is a parallel version of Korat and aims to take advantage of multi-processor and multicore systems available. Fast Korat implements four optimizations which reduce the number of candidate explored to generate validate candidates and reduce the amount of time required to explore each candidate. This report also presents the execution time results for generating test candidates for binary tree, doubly linked list, and sorted singly linked list, from their respective predicates. / text

On January 14, 2004, President George W. Bush announced the Vision for Space Exploration (VSE). The goals of the vision include developing a new generation launch capability while completing assembly of the International Space Station (ISS) and retiring the Space Shuttle by 2010. In support of this goal, the Space Shuttle Program (SSP) initiated evaluation of hardware, infrastructure, and workforce skill mix needed to continue Space Shuttle flights until the projected 2010 retirement. The SSP also studied how NASA will deploy personnel from, and use the facilities of, the SSP to ensure that the Space Shuttle operates safely through its final flight, and to ensure personnel and facilities from the SSP are effectively transitioned to NASA’s exploration programs. NASA funding, like other federal agencies, is affected by various factors including domestic and international political environments, current and emerging technologies available to meet agency goals, and sustainability and potential economic return of federal expenditures. In this paper I will present a retrospective analysis of federal budget allocations to NASA as a percentage of the Federal Budget from years 1958 to 2010 (adjusted to 1979 dollars). The classic method for calculating net present value (NPV) is not well suited for projecting potential value of future R&D technologies. A quantitative analysis of R&D technologies transferred to private industry will be presented, as well as a description of a method of evaluating their significance will discussed relative to current budgetary considerations will likely for past, current and upcoming funding cycles. The opportunity at hand for NASA’s transition from SSP to Constellation in support of the VSE initiative is to advocate their culture as R&D innovators and emphasize the future benefit of increased funding. / text

Nowadays the ever increasing algorithmic complexity of embedded applications requires the designers to turn towards heterogeneous and highly integrated systems denoted as SoC (System-on-a-Chip). These architectures may embed CPU-based processors, dedicated datapaths as well as recon gurable units. However, embedded SoCs are submitted to stringent requirements in terms of speed, size, cost, power consumption, throughput, etc. Therefore, new computing paradigms are required to ful l the constraints of the applications and the requirements of the architecture. Recon gurable Computing is a promising paradigm that provides probably the best trade-o between these requirements and constraints. Dynamically recon gurable architectures are their key enabling technology. They enable the hardware to adapt to the application at runtime. However, these architectures raise new challenges in SoC design. For example, on one hand, designing a system that takes advantage of dynamic recon guration is still very time consuming because of the lack of design methodologies and tools. On the other hand, scheduling hardware tasks di ers from classical software tasks scheduling on microprocessor or multiprocessors systems, as it bears a further complicated placement problem. This thesis deals with the problem of scheduling online real-time hardware tasks on Dynamically Recon gurable Hardware Devices (DRHWs). The problem is addressed from two angles : (i) Investigating novel algorithms for online real-time scheduling/placement on DRHWs. (ii) Scheduling/Placement algorithms library for RTOS-driven Design Space Exploration (DSE). Regarding the first point, the thesis proposes two main runtime-aware scheduling and placement techniques and assesses their suitability for online real-time scenarios. The first technique discusses the impact of synthesizing, at design time, several shapes and/or sizes per hardware task (denoted as multi-shape task), in order to ease the online scheduling process. The second technique combines a looking-ahead scheduling approach with a slots-based recon gurable areas management that relies on a 1D placement. The results show that in both techniques, the scheduling and placement quality is improved without signi cantly increasing the algorithm time complexity. Regarding the second point, in the process of designing SoCs embedding recon gurable parts, new design paradigms tend to explore and validate as early as possible, at system level, the architectural design space. Therefore, the RTOS (Real-Time Operating System) services that manage the recon gurable parts of the SoC can be re fined. In such a context, gathering numerous hardware tasks scheduling and placement algorithms of various complexity vs performance trade-o s in a kind of library is required. In this thesis, proposed algorithms in addition to some existing ones are purposely implemented in C++ language, in order to insure the compatibility with any C++/SystemC based SoC design methodology.