ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Data-aided symbol synchronization for bursty communications utilizes a predetermined modulation sequence, i.e., a preamble, preceding the payload. For effective symbol synchronization, this preamble must be designed in accordance with the modulation format. In this paper, we analyze preambles for shaped offset quadrature phase-shift keying (SOQPSK) waveforms. We compare the performance of several preambles by deriving the Cram´er-Rao bound (CRB), and identify a desirable one for the Telemetry Group variant of SOQPSK. We also demonstrate, via simulation, that the maximum likelihood estimator with this preamble approaches the CRB at moderate signal-to-noise ratio.

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In this dissertation, the problem of symbol timing synchronization for the following three different communication systems is studied: 1) conventional single-carrier transmissions with single antenna in both transmitter and receiver; 2) single-carrier transmissions with multiple antennas at both transmitter and receiver; and 3) orthogonal frequency division multiplexing (OFDM) based IEEE 802.11a wireless local area networks (WLANs). For conventional single-carrier, single-antenna systems, a general feedforward symbol-timing estimation framework is developed based on the conditional maximum likelihood principle. The proposed algorithm is applied to linear modulations and two commonly used continuous phase modulations: MSK and GMSK. The performance of the proposed estimator is analyzed analytically and via simulations. Moreover, using the newly developed general estimation framework, all the previously proposed digital blind feedforward symbol timing estimators employing second-order statistics are cast into a unified framework. The finite sample mean-square error expression for this class of estimators is established and the best estimators are determined. Simulation results are presented to corroborate the analytical results. Moving on to single-carrier, multiple-antenna systems, we present two algorithms. The first algorithm is based on a heuristic argument and it improves the optimum sample selection algorithm by Naguib et al. so that accurate timing estimates can be obtained even if the oversampling ratio is small. The performance of the proposed algorithm is analyzed both analytically and via simulations. The second algorithm is based on the maximum likelihood principle. The data aided (DA) and non-data aided (NDA) ML symbol timing estimators and their cor- responding CCRB and MCRB in MIMO correlated ??at-fading channels are derived. It is shown that the improved algorithm developed based on the heuristic argument is just a special case of the DA ML estimator. Simulation results under different operating conditions are given to assess and compare the performances of the DA and NDA ML estimators with respect to their corresponding CCRBs and MCRBs. In the last part of this dissertation, the ML timing synchronizer for IEEE 802.11a WLANs on frequency-selective fading channels is developed. The proposed algorithm is compared with four of the most representative timing synchronization algorithms, one specically designed for IEEE 802.11a WLANs and three other algorithms designed for general OFDM frame synchronization.

In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.

In this thesis, symbol timing recovery in MSK signals is investigated making use of matched filtering. A decision-directed symbol synchronizer cascaded with an MLSE receiver is proposed for fine timing. Correlation (matched filter) method is used to recover the timing epoch from the tentative decisions obtained from the Viterbi algorithm. The fractional delays are acquired using interpolation and an iterative maximum search process. In order to investigate the tracking performance of the proposed symbol synchronizer, a study is carried out on three possible optimum timing phase criteria: (i) Mazo criterion, (ii) the minimum squared ISI criterion (msISI), and (iii) the minimum BER criterion. Moreover, a discussion is given about the timing sensitivity of the MLSE receiver. The performance of the symbol synchronizer is assessed by computer simulations. It is observed that the proposed synchronizer tracks the variations of the channels almost the same as the msISI criterion. The proposed method eliminates the cycle slips very succesfully and is robust to frequency-selective multipath fading channel conditions even in moderate signal-to-noise ratios.

Maximum likelihood symbol timing estimation for communication over a frequency non-selective MIMO fading channel is developed. The cases of known data (data-aided estimation) and unknown data (non-data-aided estimation) together with known channel and unknown channel are considered. The analysis shows that the log-likelihood functions and their approximations can be interpreted as SISO log-likelihood functions operating on each of the receive antennas. Previously published symbol timing estimators are shown to be special cases of the more general framework presented. Architectures based on both block processing and sequential processing using a discrete-time phase-locked loop are summarized. Performance examples over a MIMO channel based on measured data and on a simple stochastic MIMO channel model are given. These examples show that the mean-squared error performance of these techniques is not strongly dependent on the MIMO channel and is able to reach the Cramer Rao bound when sufficient complexity is applied.

The Universal Classifier Synchronizer (UCS) is a Cognitive Radio system/sensor that can detect, classify, and extract the relevant parameters from a received signal to establish physical layer communications using the received signal's profile. The current implementation is able to identify signals including AM, FM, MPSK, QAM, MFSK, and OFDM. The system is constructed to run on a Universal Software Radio Peripheral (USRP) with the GNU Radio software toolkit and also runs on an Anritsu™ signal analyzer. In both prototypes, the UCS system runs on a host computer's General Purpose Processor (GPP) and is constructed in Matlab™. The aim is to then create a portable and standalone version of the UCS system as an intermediate step towards building a future commercial implementation. This application and particular implementation aims to run on a Lyrtech SFF SDR platform and uses its FPGA and DSP modules for implementation. This platform is one of the more advanced SDR platforms available, and the aim is to develop parts of the UCS system to run on this platform. The aim is to eventually develop the complete UCS cognitive radio system on the Lyrtech SFF SDR platform that can act as a standalone portable cognitive radio system. The modules created and implanted/implemented on the SDR hardware are the Bandwidth Estimation, and Symbol Timing & Coarse Classification modules. This is the system decision path towards classification, synchronization, and demodulation of digital phase modulated signals (QAM and MPSK signal types) and also analog signals. The Digital Receiver Module (DRM) is implemented on the FPGA and takes care of all the digital down conversions, mixing, decimation, and low pass filtering. The FPGA is connected to the DSP module via a bus subsystem where the DSP receives real-time base-band complex IQ samples for further signal processing. The main UCS algorithm runs on the platform's DSP and is compiled from executable embedded C-code. Therefore, this system can then be implemented on virtually any setup that has an RF front end, digital receiver module, and processing module that will execute floating and fixed point C-code with minor changes. / Master of Science

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Sandia National Laboratories (SNL) currently achieves a bandwidth efficiency (h ) of 0.5 to 1.0 bps/Hz by using traditional modulation schemes, such as, BPSK and QFSK. SNL has an interest in increasing the present bandwidth efficiency by a factor of 4 or higher with the same allocated bandwidth (about 10 MHz). Simulations have shown that 32- QAM trellis-coded modulation (TCM) gives a good bit error rate (BER) performance, and meets the requirements as far as the bandwidth efficiency is concerned. Critical to achieving this is that the receiver be able to achieve timing synchronization. This paper examines a particular timing recovery algorithm for all-digital receivers. Timing synchronization in a digital receiver can be achieved in different ways. One way of achieving this is by interpolating the original sampled sequence to produce another sampled sequence synchronized to the symbol rate or a multiple of the symbol rate. An adaptive sampling conversion algorithm which performs this function was developed by Floyd Gardner in 1993. In the present work, his algorithm was applied to two different modulation schemes, BPSK and 4-ary PAM. The two schemes were simulated in the presence of AWGN and ISI along with Gardner’s algorithm for timing recovery, and a fractionally spaced equalizer (T/2 FSE) for equalization. Simulations show that the algorithm gives good BER performance for BPSK in all the situations, and at different sampling frequencies, but unfortunately poor performance for the 4-ary PAM scheme. This indicates that Gardner’s algorithm for sampling conversion is not suitable for multi-level signaling schemes.

Η παρούσα διπλωματική εργασία αφορά στην πειραματική αξιολόγηση του μηχανισμού ανάκτησης ρυθμού συμβόλου για ψηφιακούς δέκτες τεχνολογίας SDR που λαμβάνουν δεδομένα μέσω δορυφόρου. Η ορολογία SDR/SR (Software Defined Radio/Software Radio) χρησιμοποιείται για να χαρακτηρίσει τους πομποδέκτες που μπορούν να καθορίζουν σημαντικές παραμέτρους τους και βασικές αρχές της λειτουργίας τους μέσω αναβάθμισης ή ενημέρωσης του λογισμικού τους. Ο μηχανισμός ανάκτησης του ρυθμού συμβόλου (Symbol Timing Recovery, STR) αναπτύχθηκε στα πλαίσια της διδακτορικής διατριβής του διδάκτορος Παναγιώτη Σαββόπουλου. Η παρούσα εργασία μελετά τη σύγκλιση του βρόχου υπό συνθήκες παραμένοντος σφάλματος συχνότητας καθώς επίσης και τον προσδιορισμό του λόγου σήματος προς θόρυβο στην έξοδο του βρόχου κάνοντας χρήση ενός νέου μεγέθους, metric, το οποίο έχει εισαχθεί στα πλαίσια της προαναφερθείσας διδακτορικής διατριβής, υπό συνθήκες λευκού Gaussian θορύβου. Το μέγεθος αυτό είναι σε θέση να δώσει αξιόπιστα αποτελέσματα στις ενδιάμεσες υπομονάδες του δέκτη υπό συνθήκες παραμένοντος σφάλματος συχνότητας. Στην παρούσα εργασία μελετώνται οι QPSK, 8PSK, 16-APSK και 32-APSK διαμορφώσεις διότι αυτές οι διαμορφώσεις χρησιμοποιούνται από το πρότυπο DVB-S2. / The purpose of this project is the experimental evaluation of a mechanism for the symbol timing recovery which is used in digital Software Defined Radio receivers. SDR/SR (Software Defined Radio/Software Radio) technology is used to characterise the transmitters and the receivers which are able to determine important parameters and basic primciples for their function through upgrade or briefing of their software. The symbol timing recovery mechanism (STR) was developped in terms of the doctora of dr Panagiotis Savopoylos. The precent project examines the loop’s convergence when there is frequency error as well as the signal to noise ratio in the output of STR with the use of a new size, metric, which was also developped in terms of the doctora which was mentioned before, when there is white Gaussian noise. The metric is able to give reliable results in the intermediate stages of the receiver when there is frequency error. In the precent project are examined the QPSK, 8PSK,16-APSK, 32-APSK modulations because these modulations are used in DVB-S2 standard.

Aeronautical telemetry systems have historically been implemented with constant envelope modulations like CPM. Shifts in system constraints including reduced available bandwidth and increased throughput demands have caused many in the field to reevaluate traditional methods and design practices. This work examines the costs and benefits of using APSK for aeronautical telemetry instead of CPM. Variable rate turbo codes are used to improve the power efficiency of 16- and 32-APSK. Spectral regrowth in nonlinear power amplifiers when driven by non-constant envelope modulation is also considered. Simulation results show the improved spectral efficiency of this modulation scheme over those currently defined in telemetry standards. Additionally, the impact of transitioning from continuous transmission to burst-mode is considered. Synchronization loops are ineffective in burst-mode communication. Data-aided feed forward algorithms can be used to estimate offsets in carrier phase, frequency, and symbol timing between the transmitter and the receiver. If a data-aided algorithm is used, a portion of the transmitted signal is devoted to a known sequence of pilot symbols. Optimum pilot sequences for the three synchronization parameters are obtained analytically and numerically for different system constraints. The alternating sequence is shown to be optimal given a peak power constraint. Alternatively, synchronization can be accomplished using blind algorithms that do not rely on a priori knowledge of a pilot sequence. If blind algorithms are used, the observation interval can be longer than for data-aided algorithms. There are combinations of pilot sequence length and packet length where data-aided algorithms perform better than blind algorithms and vice versa. The conclusion is that a sequential arrangement of blind algorithms operating over an entire burst performs better than a CRB-achieving data-aided algorithm operating over a short pilot sequence.