The rapid growth of communication technology with the success of internet, has brought huge profits and great convenience to our daily life. Computer networks can be built using either wired or wireless technologies. It will be an important issue that how to select a medium for the transmission. Wired Ethernet has been the traditional choice in most of the networks. However, it has to deploy the Ethernet wires. For the wired internet networks, the power line communication (PLC) technology will be an alternative choice. In this wire-line communication system, the power line network is used as the transmission medium. Therefore, computer networks can work on the existing power line system. No extra new transmission infrastructure is needed. So far, several PLC standards are available, shch as X-10, CEBus(Consumer Electronic Bus), Echonet and Homeplug. This thesis studies the Homeplug AV specification developed by the Homeplug powerline Alliance. By employing MATLAB/Simulink, we build up a PLC baseband transmission model and simulation platform. We carry out the Homeplug AV baseband transmission performance in system level on this platform. The Homeplug AV adopts 3072-point FFT which is not the power of two. It will be a challenge to design the 3072-point FFT processor. Here, we use Xilinx System Generator to design and implement the 3072-point FFT processor. The function verification of the implemented 3072-point FFT processor for Homeplug AV system is carried out by simulation.

<p>Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. </p> / <p>The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.</p>

No description available.

Orientador: Luis Geraldo Pedroso Meloni / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T05:58:36Z (GMT). No. of bitstreams: 1 LemesFilho_JoseMatias.pdf: 2987431 bytes, checksum: 93fc757a06215b93a08427d2f33f88a2 (MD5) Previous issue date: 2009 / Resumo: Este trabalho descreve o estudo, a pesquisa e compilação de técnicas de otimização de códigos em FPGA (Field Programmable Gate Arrays) utilizando uma ferramenta de prototipagem rápida. Para isso, foram implementados alguns algoritmos para auxiliar na apresentação e avaliação de quatro técnicas de otimização: uso de recursos alternativos, multiplexação no tempo, algoritmos alternativos e mudança da freqüência sistêmica. As principais contribuições do presente trabalho foram: compilar em um único documento diversas técnicas para geração eficiente de códigos de processamento digital de sinais; o estudo das etapas de fluxo de projeto baseado em ferramentas de prototipagem rápida; implementações de diversos algoritmos para demonstrar as técnicas de otimização, visando-se o estudo da minimização da área de ocupação em FPGA. Com o uso das técnicas pode-se alcançar uma redução de área da FPGA de até 90%, conforme a complexidade do sistema alvo. / Abstract: This work describes the study, research and compilation of programming optimization techniques for FPGA (Field Programmable Gate Arrays) using a tool technology for rapid prototyping. For this purpose, some algorithms have been implemented to help the presentation and evaluation of four optimization techniques: alternative resources usage, time multiplexing, alternative algorithms and systemic frequency change. The main contributions of this work are: compilation in one document several efficient techniques for generation code in digital signal processing; study of the phases of design flow were based on rapid prototyping tools; implementations of several algorithms to demonstrate the optimization techniques, looking for the minimization of the FPGA occupation area. With the use of these techniques, it is possible to reach a FPGA area reduction of up to 90%, depending of the complexity of the target system. / Universidade Estadual de Campi / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm. In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without using Matlab and the XSG. After generating code the results were synthesised, analysed and compared. The frequency estimator basically contains an FFT, a windowing function and a sorting algorithm used to enable analyse of two real signals simultaneously. There were however problems during generation of the VHDL code and the model had to be broken into smaller parts containing only a 16-point FFT. The results of comparison in this report are based on models containing only this 16-point FFT and they show a small advantage for the System Generator according to the resource usage report generated during synthesis. Designing models for generation using Xilinx Blockset can create a lot of wiring between components. The reason for this is that the System Generator and Xilinx Blockset today is a new tool, not completely developed. There are many components found in simulink, Matlab that could not be found in Xilinx Blockset, this is however being improved. Another problem is long time for simulation and errors during generation. My opinion is that when used for smaller systems and with further development the System Generator can be a useful facility in designing digital electronics.

In this thesis, we consider an analog antenna combining architecture for a MIMO wireless transceiver, while pointing out its advantages with respect to the traditional MIMO architectures. In the first part of this work, we focus on the transceiver design, especially the calculation of the beamformers that must be applied at the RF. This analysis is performed in an OFDM system under different assumptions on the channel state information. As a result, several criteria and algorithms for the selection of the beamformers are proposed. In the second part, we address the FPGA design and implementation of a baseband processor for this architecture. This baseband processor is based on the standard IEEE 802.11a. Finally, some real-time tests of the implemented baseband processor are carried out both in stand-alone configuration and also with the whole physical layer setup. / En esta tesis consideramos una arquitectura de combinación analógica de antenas para una estación inalámbrica MIMO, señalando las ventajas de ésta con respecto a la arquitectura tradicional MIMO. En la primera parte de este trabajo analizamos el cálculo de los pesos que se deben aplicar en RF. Este análisis es realizado para un sistema OFDM bajo diferentes suposiciones sobre el conocimiento del canal en el transmisor. Como resultado, se ofrecen varios criterios y algoritmos para el cálculo de los pesos. La segunda parte se centra en el diseño y la implementación FPGA de un procesador banda base para esta arquitectura. Este procesador está basando en el estándar IEEE 802.11a. Finalmente se llevan a cabo algunos experimentos en tiempo-real del procesador banda base. Estos experimentos se han realizado tanto con el procesador aislado como integrado en el resto de la capa física del sistema.

<p>This Master’s Thesis is an evaluation of the software Xilinx System Generator (XSG) and blockset for Matlab. XSG is a module to simulink developed by Xilinx in order to generate VHDL code directly from functions implemented in Matlab. The evaluation was made at Saab Avionics AB in Järfälla, north of Stockholm. </p><p>In order to investigate the performance of this new module XSG to simulink, a model of a frequency estimator often used in digital radar receivers were implemented in Matlab using XSG. Engineers working at SAAB Avionics implemented the same application directly in VHDL, without using Matlab and the XSG. After generating code the results were synthesised, analysed and compared. </p><p>The frequency estimator basically contains an FFT, a windowing function and a sorting algorithm used to enable analyse of two real signals simultaneously. There were however problems during generation of the VHDL code and the model had to be broken into smaller parts containing only a 16-point FFT. The results of comparison in this report are based on models containing only this 16-point FFT and they show a small advantage for the System Generator according to the resource usage report generated during synthesis. </p><p>Designing models for generation using Xilinx Blockset can create a lot of wiring between components. The reason for this is that the System Generator and Xilinx Blockset today is a new tool, not completely developed. There are many components found in simulink, Matlab that could not be found in Xilinx Blockset, this is however being improved. Another problem is long time for simulation and errors during generation. </p><p>My opinion is that when used for smaller systems and with further development the System Generator can be a useful facility in designing digital electronics.</p>

Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2017-12-01T23:34:00Z No. of bitstreams: 1 DanielHolandaNoronha_DISSERT.pdf: 2617561 bytes, checksum: 88cfc246d074eabfd971d5b81edbf109 (MD5) / Approved for entry into archive by Arlan Eloi Leite Silva (eloihistoriador@yahoo.com.br) on 2017-12-05T21:07:17Z (GMT) No. of bitstreams: 1 DanielHolandaNoronha_DISSERT.pdf: 2617561 bytes, checksum: 88cfc246d074eabfd971d5b81edbf109 (MD5) / Made available in DSpace on 2017-12-05T21:07:18Z (GMT). No. of bitstreams: 1 DanielHolandaNoronha_DISSERT.pdf: 2617561 bytes, checksum: 88cfc246d074eabfd971d5b81edbf109 (MD5) Previous issue date: 2017-11-20 / A import?ncia do uso de FPGAs como aceleradores vem crescendo fortemente nos ?ltimos anos. Companhias como Amazon e Microsoft est?o incorporando FPGAs em seus data centers, objetivando especialmente acelerar algoritmos em suas ferramentas de busca. No centro dessas aplica??es est?o algoritmos de aprendizado de m?quina, como ? o caso da M?quina de Vetor de Suporte (SVM). Entretanto, para que essas aplica??es obtenham a acelera??o desejada, o uso eficiente dos recursos das FPGAs ? necess?rio. O projeto possui como objetivo a implementa??o paralela em hardware tanto da fase feed-forward de uma M?quina de Vetores de Suporte (SVM) quanto de sua fase de treinamento. A fase feed-forward (infer?ncia) ? implementada utilizando o kernel polinomial e de maneira totalmente paralela, visando obter a m?xima acelera??o poss?vel ao custo de uma maior utiliza??o da ?rea dispon?vel. Al?m disso, a implementa??o proposta para a infer?ncia ? capaz de computar tanto a classifica??o quanto a regress?o utilizando o mesmo hardware. J? o treinamento ? feito utilizando Otimiza??o Sequencial M?nima (SMO), possibilitando a resolu??o da complexa otimiza??o da SVM atrav?s de passos simples. A implementa??o da SMO tamb?m ? feita de modo extremamente paralelo, fazendo uso de t?cnicas para acelera??o como a cache do erro. Ademais, o Kernel Amig?vel ao Hardware (HFK) ? utilizado para diminuir a ?rea utilizada pelo kernel, permitindo que um n?mero maior de kernels seja implementado em um chip de mesmo tamanho, acelerando o treinamento. Ap?s a implementa??o paralela em hardware, a SVM ? validada por simula??o e s?o feitas an?lises associadas ao desempenho temporal da estrutura proposta, assim como an?lises associadas ao uso de ?rea da FPGA. / The importance of Field-Programmable Gate Arrays as compute accelerators has dramatically increased during the last couple of yers. Many companies such as Amazon, IBM and Microsoft included FPGAs in their data centers aiming to accelerate their search engines. In the center of those applications are many machine learning algorithms, such as Support Vector Machines (SVMs). For FPGAs to thrive in this new role, the effective usage of FPGA resources is required. The project?s main goal is the parallel FPGA implementation of both the feed-forward phase of a Support Vector Machine as well as its training phase. The feed-forward phase (inference) is implemented using the polynomial kernel in a highly parallel way in order to obtain maximum throughput at the cost of some extra area. Moreover, the inference implementation is capable of computing both classification and regression using a single hardware. The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO implementation is also highly parallel and uses some acceleration techniques, such as the error cache. Moreover, the Hardware Friendly Kernel (HFK) is used in order to reduce the kernel?s area, enabling the increase in the number of kernels per area. After the parallel implementation in hardware, the SVM is validated by simulation. Finally, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGA?s area usage are performed.

FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histogram as a test case to investigate the efficiency of three different tools, HDL Coder in MATLAB, HDL Coder in Simulink and System Generator for DSP in comparison to the direct development of the same histogram in Vivado using Verilog. How to write and structure code in these tools for proper functionality was also examined. It has been found that all tools deliver an operation frequency comparable to a direct implementation in Verilog, decreased resource usage, a development time which decreased by 27% (HDL Coder in MATLAB), 45% (System Generator) and 64% (HDL Coder in Simulink) but at the cost of increased power consumption. Instructions for how to use all three tools has been collected and summarised. / I ingångssteget på ett mätsystem är det av intresse att använda en FPGA för att uppnå höga hastigheter på de oundvikliga datafiltrering och sorterings algoritmer som körs. Ett problem med FPGAer är att utvecklingen ställer höga krav på specifik kunskap gällande utvecklingsspråk och miljöer vilket för en person specialiserad inom t.ex. signalbehandling kan saknas helt. HLS är en metodik där högnivåspråk kan användas för digital design genom att nyttja ett verktyg för automatgenerering av kod. I detta arbete har utveckling av ett histogram använts som testfall för att utvärdera effektivitet samt designmetodik av tre olika HLS verktyg, HDL Coder till MATLAB, HDL Coder till Simulink och System Generator for DSP. Utvecklingen i dessa verktyg har jämförts mot utvecklingen av samma histogram i Vivado, där språket Verilog använts. Arbetets slutsater är att samtliga verktyg som testats leverar en arbetsfrekvens som är jämförbar med att skriva histogrammet direkt i Verilog, en minskad resursanvändning, utvecklingstid som minskat med 27% (HDL Coder i MATLAB), 45% (System Generator) och 64% (HDL Coder i Simulink) men med en ökad strömförbrukning. En sammanställning av instruktioner för utveckling med hjälp av verktygen har även gjorts.

專家決策支援系統（Expert Decision Support System）是一種結合專家 系統與決策支援系統功能於一體的電腦化資訊系統；它同時具備有處理定 性資料與定量資料的能力，可以進行各種知識法則的推論及數量模式的執 行與分析，以完整的支援問題之求解過程。 / The expert decision support system(EDSS) is a computer-based nformation system which integrates functions of the expert systemnd the decision support system. EDSS, which is capable ofrocessing symbolic and numerical data, provides the