Zugl.: Berlin, Techn. Univ., Diss., 2009

Future smart grid systems will intelligently monitor and control energy flows in order to improve the efficiency and reliability of power delivery. This monitoring and control requires low-power, low-cost and highly reliable two-way communications between customers and utilities. To enable these two-way communication links, powerline communication (PLC) systems are attractive because they can be deployed over existing outdoor and indoor power lines. Power lines, however, have traditionally been designed for one-directional power delivery and remain hostile environments for communication signal propagation. In particular, non-Gaussian noise that is dominated by asynchronous impulsive noise and periodic impulsive noise, is one of the primary factors that limit the communication performance of PLC systems. For my PhD dissertation, I propose transmitter and receiver methods to mitigate the impact of asynchronous impulsive noise and periodic impulsive noise, respectively, on PLC systems. The methods exploit sparsity and/or cyclostationarity of the noise in both time and frequency domains, and require no or minor training overhead prior to data transmission. Compared to conventional PLC systems, the proposed transceivers achieve dramatic improvement (up to 1000x) in coded bit error rates in simulations, while maintaining similar throughput. / text

The initial design of an OFDM transceiver is described and the simulations using MATLAB’s Simulink Software and other FGPA based tools are presented. All components of a modern OFDM system were implemented in Simulink to provide an understanding of the various components of an OFDM system, provide a proof of concept in the design, and measure the theoretical performance of the system. In an effort to build the transceiver, the FFT and randomizer components were implemented in verilog and were successfully simulated using ModelSim Altera Starter Edition 6.5b. A commercially available OFDM core, which did not include forward error correction, was simulated to measure the performance of an OFDM system within Altera Stratix III devices and determine the overall logic utilization for OFDM modulation and demodulation. The goals of this report are to describe in detail the general effort made by the author to build an OFDM transceiver and serve as a driver for its eventual FPGA implementation. / text

White LEDs (Light Emitting Diodes) in Visible Light Communication (VLC) is an emerging technology that is being researched so it can eventually be used for common communications systems. LEDs have a number of advantages, one of which is long life expectancy. However, like many emerging technologies, VLC has many technical issues that need to be addressed. We proposed an optical indoor wireless communication system that used white LEDs like plug-in devices. We developed a practical implementation of VLC and demonstrated it experimentally. In particular we focused on designing a prototype of VLC that can be used without having to make major changes to the present infrastructure with two types of protocol — namely RS-232 and USB — for data transmission.

Zugl.: Dresden, Techn. Univ., Diss., 2005

Zugl.: Dresden, Techn. Universiẗat, Diss., 2008.

Zugl.: Erlangen, Nürnberg, Univ., Diss., 2008

abstract: The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

abstract: The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system. Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems. The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems. / Dissertation/Thesis / Doctoral Dissertation Engineering 2017

abstract: Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test times, which complicates load-board design, debug, and diagnosis. Second, high frequency operation necessitates the use of expensive equipment, resulting in higher per second test time cost compared with mixed-signal or digital circuits. Moreover, in terms of the non-recurring engineering cost, the need to measure complex specfications complicates the test development process and necessitates a long learning process for test engineers. Test time is dominated by changing and settling time for each test set-up. Thus, single set-up test solutions are desirable. Loop-back configuration where the transmitter output is connected to the receiver input are used as the desirable test set- up for RF transceivers, since it eliminates the reliance on expensive instrumentation for RF signal analysis and enables measuring multiple parameters at once. In-phase and Quadrature (IQ) imbalance, non-linearity, DC offset and IQ time skews are some of the most detrimental imperfections in transceiver performance. Measurement of these parameters in the loop-back mode is challenging due to the coupling between the receiver (RX) and transmitter (TX) parameters. Loop-back based solutions are proposed in this work to resolve this issue. A calibration algorithm for a subset of the above mentioned impairments is also presented. Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. EVM is analytically related to system impairments, which are typically measured in a production test i environment. Thus, EVM test can be eliminated from the test list if the relations between EVM and system impairments are derived independent of the circuit implementation and manufacturing process. In this work, the focus is on the WLAN standard, and deriving the relations between EVM and three of the most detrimental impairments for QAM/OFDM based systems (IQ imbalance, non-linearity, and noise). Having low cost test techniques for measuring the RF transceivers imperfections and being able to analytically compute EVM from the measured parameters is a complete test solution for RF transceivers. These techniques along with the proposed calibration method can be used in improving the yield by widening the pass/fail boundaries for transceivers imperfections. For all of the proposed methods, simulation and hardware measurements prove that the proposed techniques provide accurate characterization of RF transceivers. / Dissertation/Thesis / Ph.D. Electrical Engineering 2013