The aim of this master thesis is to design a wireless system which would be primarily used for a control of stage lighting. Our idea is to establish wireless links, that will carry DMX512 protocol, between individual lighting devices based on wireless transceiver nRF2401A. The foundation of our project comes from a previous design, which was not completely suitable for a practical use because of its rather large proportions and a short RF range. The project resolves the issue of relatively short range coverage through the deployment of RF amplifier RF5722. In the same tme, it also takes into account other technical aspects such as the use of antenas with a higher gain, front-end circuits or increased transmission reliability through frequency hopping scheme. Proper attention is also given to a minimalization of the module dimensions by using SMD components and layout adjustements, so it would be possible to place the whole board inside XLR connector. Set of printed circuit boards with the specified characteristics, which is the expected outcome of our project, were designed with Eagle PCB design environment.

This work comprises an approximation of the energy consumption of the transceiver circuit in a single board computer. Single board computers, such as the Raspberry Pi 4 Model B that is used here, are usually cheap and therefore more accessible. This method of estimation does not use any other hardware which gives it an advantage compared to many other methods that use expensive measurement equipment, but it unfortunately comes with certain trade-offs, like accuracy, to name one example. One area where this approximation method could be applied is for optimizing the energy efficiency of wireless sensor networks. The method can be divided into two main parts, firstly the transceiver’s active transmission and reception states are profiled and then a power model is chosen and adapted to suit the transceiver as well as possible. These two steps are then combined and results in an energy consumption approximation. The evaluation of the results showed that the estimations are reasonable according to the most relevant findings on measuring a similar transceiver circuit, but there are also limitations that brings uncertainty to the results. More relevant studies are needed to properly assess the method of estimation and some further improvements are suggested. / Olika typer av elektroniska enheter utgör idag en stor del av många människors vardag och samhället i stort. Mobiltelefoner, laptops och olika sensorer är bara några exempel på dessa enheter som fyller viktiga funktioner i både vardag och arbete. En stor del av dem använder ett protokoll som heter IEEE 802.11ac för att kommunicera och de bör gärna göra det så energi-effektivt som möjligt. Det här arbetet undersöker energikonsumtionen hos en transceiverkrets som använder det nämnda protokollet för att skicka och ta emot datapaket. Målet med arbetet är uppskatta energikonsumtionen så väl som möjligt, med hjälp av billig och lättillgänglig hårdvara. Av den anledningen används en enkortsdator för att göra uppskattningen, mer specifikt en Raspberry Pi 4 Model B (RPi). Eftersom energiåtgången för transceiverkretsen inte kan mätas direkt från strömmen som dras av datorn, måste mjukvara skrivas för att göra uppskattningen. På det sättet undviker man behovet av dyr mätutrustning, men man måste göra avkall på till exempel noggrannhet i utbyte. Ett område där metoden eventuellt kan appliceras är för att göra trådlösa sensornätverk mer energi-effektiva. Metoden som användes för energiuppskattningen kan delas upp i två huvuddelar, förutom litteraturstudien som gjordes för att få en djupare förståelse för ämnet. Först profilerades transceiverkretsens aktiva tillstånd för transmission (TX) och mottagning (RX), som ligger i fokus för det här arbetet. Till detta användes mjukvaran perf som är ett prestandaanalyseringsverktyg som finns tillgängligt för Linuxsystem. Med hjälp av perf fick man fram längden av varje TX och RX operation i millisekunder. Sedan valdes en passande kraftmodell som anpassades för att efterlikna egenskaperna i RPi datorns transceiver så noga som möjligt. Modellen gav två olika formler för att beräkna kraftåtgången för TX respektive RX, vilket sedan multiplicerades med tidsåtgången för varje operation för att få fram energikonsumtionen. Metoden testades genom att skicka och ta emot datapaket med en storlek på 256 byte, mäta tidsåtgången, och sist räkna ut hur mycket energi som gick åt för varje enskilt paket. Resultaten presenterades med olika grafer samt en rimlighetsanalys. Slutsatsen var att resultaten verkar rimliga utgående från de mest relevanta fynden som gjordes inom ramen för litteraturstudien, men även att fler relevanta studier och mätningar behövs för att kunna göra en bättre bedömning av metodens tillförlitlighet. Slutligen framfördes förslag på eventuella förbättringar av arbetet samt områden för vidareutveckling.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / Increasing gate counts in FPGA’s create an option of offering multiple waveform demodulation and modulation within a single transponder transceiver. Differing data rates, channel schemes, and network protocols can be addressed with the flexibility of software-based demodulation and modulation. Increased satellite longevity and reliability are benefits of software-based transceiver design. Newer packaging technology offers additional capability in reducing form factor and weight of a transponder. A review of the challenges in combining each of the above to produce the next generation of transponders is the subject of this paper.

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012

Ce travail de thèse porte sur la conception et le développement de capteurs de courant adaptés aux gammes de tensions et de courants d’une installation électrique tertiaire ou industrielle. Ces nouveaux capteurs permettent d’obtenir un contrôle sur la gestion de la consommation électrique, en caractérisant un réseau grâce à la mesure de courant. Ces données transmises devront restituer les variations sur la courbe de charge de façon suffisamment détaillée pour permettre de reconnaître les équipements en fonctionnement.La première partie de ce mémoire présente les études réalisées afin de concevoir les capteurs innovants; afin de répondre aux problématiques liées aux régimes continus et transitoires. Les solutions retenues sont basées sur la technologie Rogowski qui présente notamment l’avantage d’une excellente linéarité ainsi que la mesure d’une large dynamique avec un seul dispositif. Les caractérisations de ces capteurs ont permis de valider ces modèles. La sensibilité, la linéarité et la mesure de la FFT sont certains des paramètres qu’il faut évaluer afin de caractériser les boucles de Rogowski.Les mesures effectuées sur des bancs de mesure au laboratoire et au sein de la société, avec des essais sur le terrain ont permis de spécifier et de concevoir une électronique de mise en forme, en vue d’une réalisation d’un circuit dédié. La seconde partie de ce travail concerne le conditionnement du signal. L’objectif est de rendre un capteur sans fil à l’aide de la technologie Bluetooth Low Energy et l’utilisation d’un système électronique RF utilisant un transmetteur. / Part of the CIFRE contract in collaboration with Qualisteo company, this thesis focuses on the design and development of current sensors suitable for large voltage and current ranges for a tertiary or industrial or electrical installation. These new sensors allows to obtain control over the management of power consumption, featuring a network through the current measurement. These transmitted data will return the variations of the charging curve with sufficient detail to allow to recognize the equipment in operation, limiting at the same time the size of the information provided by several orders of magnitude compared to the original signal.The first part of this thesis presents the work done in order to develop innovative sensors. The developed sensors will proposed an answer to respond to the problems related to continuous and transient states. The solutions are based on the Rogowski technology which has the advantage of excellent linearity and measuring a wide dynamic with only one device. Coil sensitivity, linearity, time domain and FFT measurements are some of the mains parameters to judge the static characteristics of the Rogowski coil.The response of this new sensors have been increased as the design and technologies have been tested. Measurements on measuring benches made by the laboratory and field trials enabled to specify and design an electronic treatment, for the specific purpose of achieving a dedicated circuit.The second part of this work concerns the signal conditioning. The aim is to make the wireless sensor using Bluetooth Low Energy technology and use of an electronic system including RF transmitter implemented.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

Universidade Federal do Cearà / Este trabalho apresenta a concepÃÃo, projeto e implementaÃÃo de um conversor CC/CC elevador para interligar um painel fotovoltaico a um banco de ultracapacitores para armazenamento de energia em substituiÃÃo Ãs baterias automotivas convencionais. Na saÃda dos ultracapacitores utiliza-se um conversor CC/CC abaixador, que fornece essa energia a um sistema de telecomunicaÃÃo para suprimento de um transceptor monocanal visando ao atendimento do serviÃo de telefonia rural/Internet em comunidades isoladas da rede pÃblica de energia. O sistema pode suprir o serviÃo de comunicaÃÃo para uma comunidade isolada da rede de energia elÃtrica por atà trÃs horas no perÃodo noturno, quando utilizado um equipamento rÃdio com cabos, conectores e antena para transmissÃo e recepÃÃo de sinal de telefonia com potÃncia de consumo de 13 W e com radiaÃÃo solar mÃdia de 5.500 W/m2/dia. Durante o dia, a energia solar à capturada por um painel fotovoltaico e armazenada em ultracapacitores atravÃs de um conversor boost. Este conversor possibilita a carga dos ultracapacitores no ponto de mÃxima potÃncia (MPP) do painel fotovoltaico. O transceptor à ativado quando se tira o fone do gancho e a alimentaÃÃo do sistema vem do painel via ultracapacitores. Caso haja ligaÃÃes durante o dia, o painel fotovoltaico supre as necessidades do equipamento transceptor. à noite, o painel utilizado nÃo gera energia suficiente para alimentar o sistema de telecomunicaÃÃo. No perÃodo noturno, caso ocorra uma chamada telefÃnica para o sistema proposto, o transceptor serà acionado, o assinante deverà retirar o monofone do gancho do aparelho telefÃnico para realizar o atendimento. Durante essa operaÃÃo o transceptor consome aproximadamente 13 W de potÃncia, que à fornecida pelos ultracapacitores, os quais estÃo interligados atravÃs do conversor buck. O sistema proposto à controlado por um microcontrolador e um circuito de controle, que procura o ponto de mÃxima potÃncia (MPP) do painel fotovoltaico, monitora o nÃvel da tensÃo dos ultracapacitores e determina o tempo de funcionamento do conversor CC/CC, que possibilita o fornecimento de energia para o transceptor pelos ultracapacitores. / This work presents the conception, design and implementation of a DC/DC boost converter to connect a photovoltaic panel to a bank of ultracapacitors for energy storage to replace the conventional automotive batteries. In the output of ultracapacitors a DC/DC step-down converter is used. This converter provides power to a telecommunication system for the supply of a single channel transceiver with the purpose of providing the services of rural telephony and Internet in isolated communities from the public energy grid. The system can provide the communication service to a isolated community from the power grid for up to three hours at night when used with radio equipment with cables, connectors and antenna for transmitting and receiving phone signal with consumption power of 13 W and with solar radiation rate of 5.500 W/m2/day. During the day solar energy is captured by a photovoltaic panel and stored in ultracapacitors through a boost converter. This converter enables ultracapacitors to charge at the maximum power point (MPP) of the photovoltaic panel. The transceiver is activated when the phone is taken off the hook and the system power comes from the panel via ultracapacitors. If there are calls during the day, the photovoltaic panel meets the needs of the transceiver. At night, the panel used does not generate enough energy to power the telecommunication system. At night, if there is a phone call to the proposed system, the transceiver will be triggered, and the subscriber should take the handset off the hook to answer an incoming call. During this operation, the transceiver consumes approximately 13 W of power, which is provided by ultracapacitors that are interconnected through the buck converter. The proposed system is controlled by a microcontroller and a control circuit which tracks the maximum power point (MPP) of the photovoltaic panel, monitors the voltage level of ultracapacitors and determines the operating time of the DC/DC converter which enables the provision of power to the transceiver by the ultracapacitors.This work presents the conception, design and implementation of a DC/DC boost converter to connect a photovoltaic panel to a bank of ultracapacitors for energy storage to replace the conventional automotive batteries. In the output of ultracapacitors a DC/DC step-down converter is used. This converter provides power to a telecommunication system for the supply of a single channel transceiver with the purpose of providing the services of rural telephony and Internet in isolated communities from the public energy grid. The system can provide the communication service to a isolated community from the power grid for up to three hours at night when used with radio equipment with cables, connectors and antenna for transmitting and receiving phone signal with consumption power of 13 W and with solar radiation rate of 5.500 W/m2/day. During the day solar energy is captured by a photovoltaic panel and stored in ultracapacitors through a boost converter. This converter enables ultracapacitors to charge at the maximum power point (MPP) of the photovoltaic panel. The transceiver is activated when the phone is taken off the hook and the system power comes from the panel via ultracapacitors. If there are calls during the day, the photovoltaic panel meets the needs of the transceiver. At night, the panel used does not generate enough energy to power the telecommunication system. At night, if there is a phone call to the proposed system, the transceiver will be triggered, and the subscriber should take the handset off the hook to answer an incoming call. During this operation, the transceiver consumes approximately 13 W of power, which is provided by ultracapacitors that are interconnected through the buck converter. The proposed system is controlled by a microcontroller and a control circuit which tracks the maximum power point (MPP) of the photovoltaic panel, monitors the voltage level of ultracapacitors and determines the operating time of the DC/DC converter which enables the provision of power to the transceiver by the ultracapacitors.This work presents the conception, design and implementation of a DC/DC boost converter to connect a photovoltaic panel to a bank of ultracapacitors for energy storage to replace the conventional automotive batteries. In the output of ultracapacitors a DC/DC step-down converter is used. This converter provides power to a telecommunication system for the supply of a single channel transceiver with the purpose of providing the services of rural telephony and Internet in isolated communities from the public energy grid. The system can provide the communication service to a isolated community from the power grid for up to three hours at night when used with radio equipment with cables, connectors and antenna for transmitting and receiving phone signal with consumption power of 13 W and with solar radiation rate of 5.500 W/m2/day. During the day solar energy is captured by a photovoltaic panel and stored in ultracapacitors through a boost converter. This converter enables ultracapacitors to charge at the maximum power point (MPP) of the photovoltaic panel. The transceiver is activated when the phone is taken off the hook and the system power comes from the panel via ultracapacitors. If there are calls during the day, the photovoltaic panel meets the needs of the transceiver. At night, the panel used does not generate enough energy to power the telecommunication system. At night, if there is a phone call to the proposed system, the transceiver will be triggered, and the subscriber should take the handset off the hook to answer an incoming call. During this operation, the transceiver consumes approximately 13 W of power, which is provided by ultracapacitors that are interconnected through the buck converter. The proposed system is controlled by a microcontroller and a control circuit which tracks the maximum power point (MPP) of the photovoltaic panel, monitors the voltage level of ultracapacitors and determines the operating time of the DC/DC converter which enables the provision of power to the transceiver by the ultracapacitors.

Carrierless amplitude and phase (CAP) modulation is generally regarded as a bandwidth efficient two-dimensional (2-D) passband line code. It is closely related to the pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) schemes. CAP has been proposed for various digital subscriber loop (DSL) systems over unshielded twisted pairs of copper wires. In this thesis, our main focus is on the minimum mean-square error (MMSE) performance of the ideal (i.e., infinite length) linear and non-linear (decision feedback) CAP receivers/equalisers in the presence of additive, coloured Gaussian noise, and/or data-like cross-talks. An in-depth analysis is given on the performance of both receiver structures. In the case of the linear receiver, one possible view of the overall CAP transceiver system which includes both data and cross-talk transmission paths is that it is a linear multiple-input multiple-output (MIMO) system. Accordingly, the existing MMSE results for a general MIMO system are applicable also to CAP systems. However, up to date, this approach was shown to be unsuccessful in the sense that the derived MMSE expressions are too complex and offer little insights. In our analysis, in order to find a more incisive MMSE expression, we reconsider the problem of minimisation of the MSEs at slicers. By exploiting the Hilbert transform pair relationship between the impulse responses of the inphase and quadrature transmit shaping filters, we are able to obtain an elegant and more meaningful MMSE expression, as well as the corresponding transfer functions of the optimum linear receive filters. In the case of the nonlinear, or decision feedback equaliser (DFE), receiver, we start our analysis with the receiver structure of a generic multidimensional (>/= 3) CAP-type system. / This receiver consists of a bank of analog receive filters, the number of which equals the dimension of the CAP line code, and a matrix of cross-connected, infinite-length, baud-spaced feedback filters. It is shown that the optimum filters and the corresponding MMSE of the DFE receiver require the factorisation of a discrete-time channel spectral matrix. This mathematically intractable step can be avoided, however, when the DFE results are specialised to a standard 2-D CAP system where we are able to again exploit the Hilbert transform pair relationship to derive a further and more useful MMSE expression. Three sets of numerical studies are given on the MMSE performance of the CAP receivers. In the first set of studies. we model the sum of all crosstalks as an additive, Gaussian noise source and select three test transmission channels over which we compare the MMSE performance of the linear and DFE receiver structures. In the second set of studies, we compare the performance of the two receiver structures, but in a data-like cross-talk environment. The results demonstrate the importance of NEXT equalisation in the design of CAP receivers operating in a NEXT dominant environment. In the final set of studies which follows from the second set of studies, we investigate the relationship between the MMSE performance of the DFE receiver and system parameters which include excess bandwidth, data rate, CAP scheme. and relative phase between the received signal and the NEXT signal. The results show that data-like cross-talks can be effectively suppressed by using a large excess bandwidth (alpha > 1 in the case of a RC transmit shaping filter) alone. / The relative phase also affect; the receiver performance. but to a lesser degree. In addition to the MMSE performance analysis. implementation issues of an adaptive linear CAP receiver are also considered. We propose a novel linear receiver by appending two fixed analog filters to the front-end of the existing adaptive linear receiver using fractionally-spaced equalisers (FSE). We show that if the analog filters are matched to the transmit shaping filters, then inphase and quadrature finite-length FSEs in the proposed receiver have the same NINISE solution. We further propose a modified least-mean-square (LMS) algorithm which takes advantage of this feature. The convergence analysis of the proposed LMS algorithm is also given. We show that the modified LMS algorithm converges approximately twice as fast as the standard LMS algorithm, given the same misadjustment, or alternatively, it halves the misadjustment, given the same initial convergence rate.

<p>The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with <em>Rocket^TMIO</em> GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz.</p> / <p>Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med <em></em>GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.</p>

Wireless communication links with multiple antennas at both the transmitter and the receiver sides, so-called multiple-input-multiple-output (MIMO)systems, are attracting much interest since they can significantly increase the capacity of band-limited wireless channels to meet the requirements of the future high data rate wireless communications. The treatment of channel state information (CSI) is critical in the design of MIMO systems. Accurate CSI at the transmitter is often not possible or may require high feedback rates, especially in multi-user scenarios. Herein, we consider the robust design of linear transceivers with imperfect CSI either at the transmitter or at both sides of the link. The framework considers the design problem where the imperfect CSI consists of a channel mean and an channel covariance matrix or, equivalently, a channel estimate and an estimation error covariance matrix. For single-user systems, the proposed robust transceiver designs are based on a general cost function of the average mean square errors. Under different CSI conditions, our robust designs exhibit a similar structure to the transceiver designs for perfect CSI, but with a different equivalent channel and/or noise covariance matrix. Utilizing majorization theory, the robust linear transceiver design can be readily solved by convex optimization approaches in practice. For multi-user systems, we consider both the communication link from the users to the access point (up-link) as well as the reverse link from the access point to the users (down-link). For the up-link channel, it is possible to optimally design robust linear transceivers minimizing the average sum mean square errors of all the data streams for the users. Our robust linear transceivers are designed either by reformulating the optimization problem as a semidefinite program or by extending the design of a single-user system in an iterative manner. Under certain channel conditions, we show that the up-link design problem can even be solved partly in a distributed fashion. For the down-link channel, a system with one receive antenna per user is considered. A robust system design is obtained by reducing the feedback load from all users to allow only a few selected users to feed back accurate CSI to the access point. We study the properties of four typical user selection algorithms in conjunction with beamforming that guarantee certain signal-to-interference-plus-noise ratio (SINR) requirements under transmit power minimization. Specifically, we show that norm-based user selection is asymptotically optimal in the number of transmitter antennas and close-to-optimal in the number of users. Rooted in the practical significance of this result, a simpler down-link system design with reduced feedback requirements is proposed. / QC 20100922