The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with RocketTMIO GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz. / Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.

The production testing cost of modern wireless communication systems, especially basestation units, is estimated to be as high as 30-40 percent of their manufacturing cost and is increasing with system complexity, high levels of device integration and scaling of CMOS process technology and operating frequencies. The major production testing challenges for RF transceivers are: (a) the high cost of automated test development because of system-level simulation difficulties and the large simulation times involved, (b) the high cost of using high-end, communication protocol-aware RF test instrumentation, and (c) lack of external test access to RF circuits embedded inside integrated transceivers. Consequently, there exists a need for developing efficient design-for-test methodologies and non-invasive system-level test techniques for wireless transceivers to reduce their test cost. This dissertation is focused towards development of new system-level alternate test methodologies for RF transceiver architectures. The research proposes using non-invasive testing techniques for RF subsystems and digital-compatible built-in testing techniques for baseband and intermediate frequency (IF) analog circuits. The objectives of this research are: (a) to develop automatic test stimulus generation algorithms that allow accurate determination of targeted RF system-level test specification values using behavioral modeling and simulation techniques, (b) to develop RF transceiver test techniques that allow testing of embedded RF systems with limited test access, while reducing the test time for complex RF and baseband system-level performance metrics (b) to significantly reduce the test instrumentation overhead for testing complex frequency-domain and modulation-domain system specifications. The feasibility and the cost benefits of using the proposed alternate test approaches have been demonstrated using 900 MHz and 1575 MHz transceiver prototypes.

The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system ¡]SCS¡^, and the design of an inter-chip capacitance coupling circuit. In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-£gm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW. In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 £gm 1P6M CMOS process. The chip area is 1045 ¡Ñ 894 £gm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.

This thesis is composed of two critical circuit designs for FlexRay ECU (Electron-ics Control Unit), i.e., a transceiver with over-current protection, and a digital over-temperature protection circuit. Regarding the transceiver with over-current protection, to reduce the glitch prob-lem, we propose to use delay cells in the transmitter. In order to avoid the transmitter current which is higher than the upperbound defined by FlexRay specifications, we propose a current comparator circuit to detect the state where the transmitter should stop sending signals. The temperature protection is required for FlexRay specifications. We propose an over-temperature circuit in the thesis. By utilizing an oscillator-based structure, fre-quency to digital converter (FDC) circuit is developed as the core of the temperature protection mechanism. It will convert the frequency signal and output the sensed tem-perature in a digital code format. The output frequency at different process and temper-ature corners show a linear feature such that the range and accuracy of temperature de-tection is enhanced.

In the high-speed indoor wireless applications, IEEE 802.11 series is the most dominating LAN standard in the current markets. In this thesis, the design issues of the IEEE 802.11a physical layer baseband system are addressed. Various key modules including Viterbi codec, FFT/IFFT module, OFDM synchronous circuit have been integrated with several other modules to constitute the entire baseband system. This system has been implemented by Verilog HDL and verified against with the C-based behavior model. In addition, it will also be prototyped and optimized on the Altera DSP FPGA Development Board. The transmission of the I, Q channel for the time domain singal is emulated by using the 10-bits AD/DA modules on the FPGA board. The experimental results shows that the gate counts of the transmitter and the receiver are 81,190 and 413,461 respectively.

Next generation wireless systems will use multiple antenna technologies, also known as multiple-input multiple-output (MIMO), to provide high data rates and robustness against fading. MIMO communication strategies for single user communication systems and their practical application in wireless networks are by now well known. MIMO communication systems, however, can benefit from multiuser processing by coordinating the transmissions to multiple users simultaneously. For numerous reasons, work on the theory of multiuser MIMO communication has yet to see broad adoption in wireless communication standards. For example, global knowledge of channel state information is often required. Such an unrealistic assumption, however, makes it difficult in practice to implement precoding techniques. Furthermore, the achievable rates of the conventional multiuser MIMO techniques are far from the theoretical performance bounds. These and other factors motivate research on practical multiuser communication strategies for the MIMO broadcast channel (point to multi-point communication) and the analysis of those strategies. The primary contributions of this dissertation are i) the development of four novel low complexity coordinated MIMO transceiver design techniques to approach the theoretical performance bound and ii) the investigation of the optimality of the proposed coordinated wireless MIMO networks. Several coordinated beamforming algorithms are proposed, where each mobile station uses quantized combining vectors or each base station uses limited feedback from the MS. The asymptotic optimality of the proposed coordinated beamforming system for the MIMO Gaussian broadcast channel is next investigated. For multi-stream transmission, a novel block diagonalized vector perturbation is proposed and the achievable sum rate upper bound of the proposed system is derived. Finally, for multi-cell environments, linear and non-linear network CBF algorithms supporting multiple cell-boundary users are proposed. The optimality of network coordinated beamforming in terms of the number of receive antennas is also investigated. / text

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / This paper describes a system framework for a multi-band, multi-mode software defined radio (MBMM SDR) being developed for next-generation telemetry applications. The system framework consists of the multi-band front-end (MBFE), the multi-mode digital radio (MMDR), and the configuration and control (C2) sub-systems. The MBFE consists of an L/S/C-band transceiver architecture that provides wideband operation, band selection, and channel tuning. The MMDR consists of the software and firmware components for high-speed digital signal processing for the telemetry waveforms. Finally, the C2 consists of the software and hardware components for system configuration, control and status. The MBFE is implemented as a standalone hardware sub-system, while the MMDR and C2 are integrated into a single hardware subsystem that utilizes state-of-the-art system-on-chip (SoC) technology. Design methodologies, hardware architectures, and system tradeoffs are highlighted to meet next-generation telemetry requirements for improved spectrum efficiency and utilizations. Approved for public release; distribution is unlimited (412TW-PA-14281).

ITC/USA 2012 Conference Proceedings / The Forty-Eighth Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2012 / Town and Country Resort & Convention Center, San Diego, California / The Serial Streaming Telemetry infrastructure is being augmented with the Telemetry Network System, which is a net-centric infrastructure requiring bi-directional communications between the test article segment and the ground station segment. As a result, future radio segments must implement transceiver architecture to support bi-directional communications. This paper presents a design methodology for a multi-band transceiver design. The design methodology is based upon the Weaver architecture to provide coarse selection between the telemetry bands. Utilization of the Weaver architecture allowed for the optimization of multiple transmitter and receiver channels into single channels to support the L/S/C-Band frequency allocations. System-level simulation is presented to evaluate the feasibility of the transceiver design for a multi-band, multi-mode software-defined radio (SDR) platform in support of Telemetry Network System.

Konstanz, FH, Diplomarb., 2004.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.