Through the use of early iNET-prototype IP Transceiver technology, Kawasaki Heavy Industries, Ltd. (KHI) has been able to communicate with a flight test vehicle. This technology provides a two-way high-capacity communication that has not been achieved with conventional telemetry. KHI has been authorized to use S-band IP Transceivers since 2014 in Japan. Then various communication tests have been performed. Last year we presented the result of the performance test of initial iNET-like RF network using a tethered aerostat at ITC. As the next phase, we have a plan of the test using a helicopter. The test is going to be conducted in September. We will present the results at ITC. This paper describes plans of the test which includes improved data backfill techniques.

This paper will present the hardware system design, development, and plan for implementation of a wireless transceiver for The Learning Labs 5000 (TLL5000) educational platform. The project is a collaborative effort by Vanessa Canac, Atif Habib, and Jason Perkey to design and implement a complete wireless system including physical hardware, physical layer (PHY-layer) modulation and filters, error correction, drivers and user-interface software. While there are a number of features available on the TLL5000 for a wide variety of applications, there is currently no system in place for transmitting data wirelessly from one circuit board to another. The system proposed in this report is comprised of an external transceiver that communicates with a software application running on the TLL-SILC 6219 ARM9 processor that is interfaced with the TLL5000 baseboard. The details of a reference design, the hardware from the GNU Radio project, are discussed as a baseline and source of information. The state of the project and hardware design is presented as well as the specific portions of the project to which Jason Perkey made significant contributions. / text

Les progrès technologiques accomplis durant ces dernières décennies dans les domaines des microsystèmes et des radiocommunications nous permettent de réaliser des composants communicants miniaturisés à faible coût afin de constituer des réseaux de capteurs sans fil. Typiquement, chacun de ces composants intègre une ou plusieurs unités de mesures (capteur), une unité de traitement de données, une unité de communication radio et une batterie. De ce fait, un nouveau domaine de recherche s’est créé pour étudier le déploiement de ces réseaux afin d’offrir des solutions de surveillance et de contrôle à distance, notamment dans des environnements complexes ou inaccessibles. Les domaines d’application de ces capteurs sont très variés, allant de la domotique au militaire en passant par le médical et les infrastructures civiles. Souvent, ces applications impliquent des contraintes sévères en terme d’autonomie qui idéalement devrait atteindre plusieurs dizaines d’années. Pour atteindre cet objectif, il est à la fois nécessaire de réduire la consommation énergétique du nœud capteur et de trouver d’autres solutions d’alimentation en énergie pour le nœud. Pour adresser ce deuxième point, la récupération d’énergie à partir de l’environnement (solaire, vibratoire, thermique, etc.) semble représenter une solution idéale pour alimenter un nœud capteur, bien que celui-ci doive s’adapter aux faibles quantités d’énergie récupérées par ces systèmes, ainsi qu’à leurs variations et intermittences. Ces travaux de thèse s’intéressent donc à la problématique de la simulation et de la réduction de la consommation des nœuds de capteurs sans-fil et autonomes en énergie. Dans un premier temps, nous avons développé la plateforme HarvWSNet, un environnement de co-simulation alliant le simulateur de réseaux WSNet et Matlab permettant ainsi la modélisation précise et la simulation hétérogène des protocoles de communication (typiquement à événements discrets) et des systèmes de récupération d’énergie (qui possèdent typiquement un comportement à temps continu). Nous avons démontré que cette plateforme permet de réaliser très rapidement des études de pré-prototypage de scénarios applicatifs de déploiement et ainsi réduire le temps de conception de ces nouvelles technologies. Grâce à la modélisation précise des éléments du système de récupération d’énergie (batterie, supercapacité, etc.) permise par cette plateforme, nous avons étudié et évalué la durée de vie de déploiements à large échelle de réseaux de capteurs alimentés par des systèmes de récupération d’énergie (solaire et éolien). La deuxième contribution de cette thèse concerne l’étude et l’implémentation de stratégies de reconfiguration dans l’interface de communication radio, qui est souvent la principale source de consommation d’énergie d’un capteur, afin de permettre au nœud et/ou au réseau de minimiser sa consommation lorsque le bilan de liaison RF est favorable. A cette fin, nous avons proposé une approche originale grâce au développement d’un simulateur de réseau dédié, EnvAdapt (basé sur WSNet). Dans cette nouvelle plateforme, des modèles de consommation des différents blocs du transceiver radio et des algorithmes de reconfiguration ont été implémentés afin d’étudier l’impact de la reconfiguration des performances de la radio sur la qualité de service et l’autonomie d’un réseau de capteurs. / Technological advances achieved over the past decade in the fields of microsystems and wireless communications have enabled the development of small size and low cost sensor nodes equipped with wireless communication capabilities able to establish a wireless sensor network (WSN). Each sensor node is typically equipped with one or several sensing unit, a data processing unit, a wireless communication interface and a battery. The challenges raised by WSNs has lead to the emergence of a new research domain which focuses on the study and deployment of such a networks in order to offer the required remote monitoring and control solutions for complex and unreachable environment. WSNs have found application in a wide range of different domains, including home and structural health monitoring, military surveillance, and biomedical health monitoring. These applications usually impose stringent constraints on the WSN lifetime which is expected to last several years. To reach this objective, it is necessary to reduce the overall energy consumption of the sensor node and to find an additional source of energy as well. To address the last point, energy harvesting from the environment seems to be a an efficient approach to sustain WSNs operations. However, energy harvesting devices, which must also be small, are usually unable to ensure a continuous operation of sensor nodes. Thus, it is necessary to adapt the WSN consumption and activity to the low and unpredictable energy scavenged. The work presented in this thesis focuses on the issue of simulation and power consumption of autonomous sensor nodes. We have first developed, HarvWSNet, a co-simulation framework combining WSNet and Matlab that provides adequate tools to accurately simulate heterogenous protocols (based on discrete-time events) and energy harvesting systems (based on continuous-time events). We have demonstrated that HarvWSNet allows a rapid evaluation of energy-harvesting WSNs deployment scenarios that may accelerate the time-to-market for these systems. Thanks to the accurate energy models (battery, supercapacitor, etc.) implemented in this platform, we have studied and evaluated a large scale deployment of solar and wind energy-harvesting WSNs. Our second contribution focuses on the implementation of energy-aware reconfiguration strategies in the radio transceiver which is usually considered as the most energy hungry component in a sensor node. These strategies are intended to reduce the excessive power consumption of the radio transceiver when the channel conditions are favorable. To this end, we have a new simulation framework called EnvAdapt (based also on WSNet) dedicated to the evaluation of reconfigurable radio transceivers for WSNs. In EnvAdapt, we have implemented the required radio transceiver behavioral and power consumption models that allows the evaluation of the impact of radio transceiver reconfiguration on the communication performance and lifetime of WSNs.

ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California / A critical element of the proposed iNET architecture is the development of a telemetry network that provides two-way communication between multiple nodes on both the ground and in the air. Conventional airborne telemetry is based on IRIG-106 Chapter 4 and provides only a serial streaming data path from the aircraft to the ground. The network-centric architecture of iNET requires not only a duplex communication link between the ground and the test article, but also a communication link that provides higher bandwidth performance, higher spectrum efficiency, and a transport environment that is capable of fully packetized Internet Protocol. This paper describes the development path followed by TTC in the implementation of its nXCVR-2000G, an OFDM 802-11a-based iNET-ready IP transceiver.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In this paper, the Miniature Data Acquisition Transceiver System (Mini-DAT), a Type II PC-Card based data acquisition and transceiver system is described. The Mini-DAT was developed by ViaSat and is currently in use at the Air Force Research Lab (AFRL) at Eglin AFB. AFRL is investigating the use of this Industrial, Scientific and Medical (ISM) band system for data collection with advanced munitions. The Mini-DAT combines the advantages of PC-Card technology with an off the shelf interfacing and packaging approach to provide a large array of capabilities in a very small package. The system provides everything needed to collect analog, discrete and digital data, process the data and transfer the data in a wireless fashion using the latest license free spread spectrum modulation technology. The advanced design of the Mini-DAT allows for operation in harsh remote environments, collecting data unattended and accessed remotely. A graphical user interface (GUI) is provided via a Windows 3.x and 95 software package that can be easily customized for specific applications. The Mini-DAT provides fast and reliable error-free data transfer over the 2.4GHz ISM communication band. It operates over a shared 80MHz bandwidth, allowing multiple access of a number of portable units operating simultaneously in the same band.

The objective of the proposed research is to create new reconfigurable RF and millimeter-wave circuit topologies that enable significant systems benefits. The market of RF systems has long evolved under a paradigm where once a system is built, performance cannot be changed. Companies have recognized that building flexibility into RF systems and providing mechanisms to reconfigure the RF performance can enable significant benefits, including: the ability support multiple modulation schemes and standards, the reduction of product size and overdesign, the ability to adapt to environmental conditions, the improvement in spectrum utilization, and the ability to calibrate, characterize, and monitor system performance. This work demonstrates X-band LNA designs with the ability to change the frequency of operation, improve linearity, and digitally control the tradeoff between performance and power dissipation. At W-band frequencies, a novel device configuration is developed, which significantly improves state-of-the-art silicon-based switch performance. The excellent switch performance is leveraged to address major issues in current millimeter-wave systems. A front-end built-in-self-test switch topology is developed to facilitate the characterization of millimeter-wave transceivers without expensive millimeter-wave equipment. A highly integrated Dicke radiometer is also created to enable sensitive measurements of thermal noise.

This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduced. It is demonstrated through theory, simulation and measurement results that the half-rate architecture can improve maximum achievable speed by a factor of 1.6. The distribution and alignment of high-frequency clocks across a wide bus of links is a signi¯cant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a bu®er into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional bu®ering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 um digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. Injection locked oscillators (ILOs) are an attractive clocking tool for low-power area- e±cient wireline receivers. In this work, we explored their use as a clock deskew element, a clock recovery unit and a programmable jitter lter. A study of both LC and ring ILOs indicates signi¯cant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting di®erent phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. First, an ILO based half-rate clock recovery technique is presented, which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is veried with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. Second, a clock forwarded 65nm CMOS receiver uses two ILOs to frequency- multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Di®erent data rates and latency mismatch between the clock and data paths are ac- commodated by a jitter tracking bandwidth that is controllable up to 300MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200MHz.

This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduced. It is demonstrated through theory, simulation and measurement results that the half-rate architecture can improve maximum achievable speed by a factor of 1.6. The distribution and alignment of high-frequency clocks across a wide bus of links is a signi¯cant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a bu®er into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional bu®ering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 um digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. Injection locked oscillators (ILOs) are an attractive clocking tool for low-power area- e±cient wireline receivers. In this work, we explored their use as a clock deskew element, a clock recovery unit and a programmable jitter lter. A study of both LC and ring ILOs indicates signi¯cant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting di®erent phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. First, an ILO based half-rate clock recovery technique is presented, which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is veried with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. Second, a clock forwarded 65nm CMOS receiver uses two ILOs to frequency- multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Di®erent data rates and latency mismatch between the clock and data paths are ac- commodated by a jitter tracking bandwidth that is controllable up to 300MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200MHz.

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

In this dissertation, we propose a circuit design and implementation of physical layer for FlexRay-based automotive communication systems which are expected to be widely used in car electronics for the years to come. To reduce the volume of electrical lines in a car and ensure safe connections, the automotive communication systems are more important than ever. FlexRay systems have been deemed as better than other existing solutions for the complicated in-vehicle networks. A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the FlexRay bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. A prototype system as well as a chip implemented by using a typical 0.18 £gm single-poly six-metal CMOS process is reported in this dissertation. Furthermore, an accurate clock signal is required in any control system, especially in the vehicle applications, where the ¡§safety¡¨ is the top priority. Because of the TDMA strategy (Time Division Multiple Access) was chosen for the FlexRay communication protocol, the system clock should not be drifting too much. A robust 20 MHz clock generator with process, supply voltage, and temperature compensation and a low-jitter 80 MHz phase-lock loop are proposed in this dissertation to reduce hostile environment effects. Finally, because the ¡§safety¡¨ and ¡§reliability¡¨ are top design requirements in the automobile electronics, we should also focus on the power supply design in the in-car communication networks. Therefore, a high tolerant and high efficiency voltage converter is proposed in this dissertation. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, this design is realized by a typical CMOS process without any thick-oxide device to tolerate input voltage range up to 3 times of the VDD voltage.