This master thesis was part of a project at the Acreo Swedish ICT AB to investigate the 28 nm FDSOI CMOS process technology for the LTE front-end application. The project has resulted in a chip that contains different test circuits such as power amplifier (PA), mixer, low noise amplifier (LNA), RF power switch, and a receiver front-end. This thesis presents the evaluation of the RF power switch. At first, a stand-alone six-stacked single pole single throw (SPST) RF power switch was designed according to Rascher, and then it was modified to single pole double throw (SPDT) RF power switch according to the requirements of the project. This report presents an overview of the FDSOI CMOS process, basic theory of the RF switch, and the evaluation techniques. The post-simulation results showed that with the proper substrate biasing and matching (50 Ω), the RF switch will provide 2.5 dB insertion loss (IL) up to 27 dBm input power and over 30 dB isolation with 30 dBm input power at 2 GHz. / Detta examensarbete har varit en del av ett projekt på Acreo Swedish ICT AB för att undersöka 28 nm FDSOI CMOS teknik för LTE front-end tillämpningar. Projektet har resulterat i ett chip som innehåller olika testkretsar: effektförstärkare, mixer, RF-effektomkoppare, LNA, och en mottagarfront-end. Denna avhandling presenterar en utvärdering av RF-omkopplaren. En SPST RF-omkopplare med sex staplade transistor konstruerades enligt Rascher. Sedan modifierades konstruktionen till en SPDT-omkoppare i enlighet med kraven för projektet. Denna rapport presenterar en översikt över FDSOI CMOS-tekniken, grundläggande teori för en RF switch samt utvärderingsmetoder. Simuleringsresultaten visade att med rätt substratbiasering och matchning (50 Ω), så ger RF-omkopplaren 2,5 dB förlust (IL) på upp till 27 dBm ineffekt och över 30 dB isolering med 30 dBm ineffekt vid 2 GHz.

This thesis presents the design and implementation of 140 GHz to 170 GHz transceivers in SiGe HBT technologies and a 95 GHz receiver in 65 nm CMOS technology. Optimization and modeling of all passive components and transistor biasing at peak-fT and peak-fMAX current densities are employed to obtain higher frequency operation of circuit blocks compared to state of the art. These circuit blocks include static and dynamic frequency dividers, voltage-controlled oscillators, and tuned mm-wave amplifiers. Design procedures for a 100 GHz static divider, a 136 GHz dynamic divider, as well as low-power divider topologies are presented. A methodology for the design of quadrature voltage-controlled oscillators in CMOS and SiGe technologies is described, together with a technique for reduced-power LO-path design. Tuned 5-stage 140 GHz, 160 GHz, and 170 GHz amplifiers with more than 15 dB in SiGe HBT technology are reported. Using these circuit building blocks, a 95 GHz receiver in 65 nm CMOS technology with 12.5 dB gain, 7 dB noise figure, and 206mW. Also, several 165 GHz transceivers are implemented in SiGe HBT technology. The 165 GHz transceivers that include an oscillator, a divider, RX, LO, and TX amplifiers, and a mixer, were designed with and without on-chip antennas. They have -3 dB conversion gain, all achieved at RF, and -3.5 dBm output power. Following that, a 140 GHz fully-integrated transceiver and a 140 GHz transceiver array with on-chip patch antennas were designed in a 0.13micron SiGe BiCMOS technology, demonstrating the highest integration levels at this frequency in silicon to date. These transceivers feature 136-145 GHz voltage-controlled oscillators, 20 dB receive-amplifiers and mixers,transmit-amplifiers with amplitude-shift keying modulation, and variable-gain IF amplifiers. At 140 GHz the transceivers have up to 32 dB conversion gain and -8 dBm output power. Wireless data transmission at 4 Gb/s was demonstrated over 1.15m with off-chip horn antennas, and over 2 cm with the on chip antennas. With on-chip antennas, the transceiver could detect a Doppler shift of as little as 25 Hz. Both transceivers were also operational in frequency-modulated continuous-wave radar mode.

This thesis presents the design and implementation of 140 GHz to 170 GHz transceivers in SiGe HBT technologies and a 95 GHz receiver in 65 nm CMOS technology. Optimization and modeling of all passive components and transistor biasing at peak-fT and peak-fMAX current densities are employed to obtain higher frequency operation of circuit blocks compared to state of the art. These circuit blocks include static and dynamic frequency dividers, voltage-controlled oscillators, and tuned mm-wave amplifiers. Design procedures for a 100 GHz static divider, a 136 GHz dynamic divider, as well as low-power divider topologies are presented. A methodology for the design of quadrature voltage-controlled oscillators in CMOS and SiGe technologies is described, together with a technique for reduced-power LO-path design. Tuned 5-stage 140 GHz, 160 GHz, and 170 GHz amplifiers with more than 15 dB in SiGe HBT technology are reported. Using these circuit building blocks, a 95 GHz receiver in 65 nm CMOS technology with 12.5 dB gain, 7 dB noise figure, and 206mW. Also, several 165 GHz transceivers are implemented in SiGe HBT technology. The 165 GHz transceivers that include an oscillator, a divider, RX, LO, and TX amplifiers, and a mixer, were designed with and without on-chip antennas. They have -3 dB conversion gain, all achieved at RF, and -3.5 dBm output power. Following that, a 140 GHz fully-integrated transceiver and a 140 GHz transceiver array with on-chip patch antennas were designed in a 0.13micron SiGe BiCMOS technology, demonstrating the highest integration levels at this frequency in silicon to date. These transceivers feature 136-145 GHz voltage-controlled oscillators, 20 dB receive-amplifiers and mixers,transmit-amplifiers with amplitude-shift keying modulation, and variable-gain IF amplifiers. At 140 GHz the transceivers have up to 32 dB conversion gain and -8 dBm output power. Wireless data transmission at 4 Gb/s was demonstrated over 1.15m with off-chip horn antennas, and over 2 cm with the on chip antennas. With on-chip antennas, the transceiver could detect a Doppler shift of as little as 25 Hz. Both transceivers were also operational in frequency-modulated continuous-wave radar mode.

Abstract¡G This thesis was consisted of two parts. Part 1 introduced the procedure for designing the RF transceiver module in an IS-95 CDMA system using link budget analysis. Part 2 was focused on a CDMA power amplifier integrated circuit design for Personal Communication Service (PCS) applications. The design procedure was introduced in detail and implemented in MMIC for using GaAs HBT foundry provided by the GCS Ltd.. The designed linear gain, output 1dB compression point and power added efficiency (PAE) are above 30 dB, 27 dBm and 36.7% respectively under a single supply voltage of 3.4 V with the help of a diode linearizer. Harmonic components were suppressed more than 26 dB without use of any filters in the output. The adjacent channel power ratio (ACPR) and the VSWR of input port are below -45 dBc and 2 respectively.

ITC/USA 2012 Conference Proceedings / The Forty-Eighth Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2012 / Town and Country Resort & Convention Center, San Diego, California / This paper details design, development and test of the Low Cost OFDM Transceiver (LCOT) LCT2-040-2200 module at S band. The goal of the project is to provide a low cost transmit and receive unit for demonstrating OFDM communication on a flight platform. The LCOT module is built to transmit and receive OFDM signals. It transmits OFDM signals at 10W power out through a custom built high power amplifier and conforms to the IEEE 802.11.g spectral emissions mask.

This report intends to impart a good understanding of routing modules used in modern transceiver systems. The radar system at RadarBolaget AB needed to have a good routing module for its newly designed transceiver antenna. In this report, studies have been done related to two majorly used routing modules in modern electronics industry; Microwave Circulator and RF/Microwave Switch. First off, different characteristics of routing modules are discussed. After having discussed important design parameters, practical design considerations for two routing modules are presented in a profound way. Theoretical knowledge for both of these two devices is presented in the beginning, followed by their practical designs using standard simulation software like HFSS and ADS. The report concludes its findings in a way that at the end of this report, reader becomes acquainted with ample information to be able to choose the best option available among all of the discussed designs. An FET RF Switch is chosen at the end of this project to be used for transceiver system which should be able to satisfy specifications specified by RadarBolaget AB. This project was carried out by two students of Master Program in Electronics/Telecommunications at Högskolan i Gävle in collaboration with RadarBolaget AB, Gävle, Sweden.

Zugl.: Erlangen, Nürnberg, Univ., Diss., 2008

Zugl.: Berlin, Techn. Univ., Diss., 2005 u.d.T.: Sezgin, Aydin: Space time codes for MIMO systems

Ulm, Univ. Diss., 2006.

abstract: Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed. Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced. Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method. Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed. Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015