Le réseau de capteurs porté est une technologie d’avenir prometteuse à multiple domaines d’application allant du médical à l’interface homme machine. Le projet BoWI a pour ambition d’évaluer la possibilité d’élaborer un réseau de capteurs utilisable au quotidien dans un large spectre d’applications et ergonomiquement acceptable pour le grand public. Cela induit la nécessité de concevoir un nœud de réseau ultra basse consommation pour à la fois convenir à une utilisation prolongée et sans encombrement pour le porteur. La solution retenue est de concevoir un nœud capable de travailler avec une énergie comparable à ce que l’état de l’art de la récolte d’énergie est capable de fournir. Une solution ASIC est privilégiée afin de tenir les contraintes d’intégration et de basse consommation. La conception de l’architecture dédiée a nécessité une étude préalable à plusieurs niveaux. Celle-ci comprend un état de l’art de la récolte d’énergie afin de fixer un objectif de budget énergie/puissance de notre système. Une étude des usages du système a été nécessaire notamment pour la reconnaissance postures afin de déterminer les cas d’applications types. Cette étude a conduit au développement d’algorithmes permettant de répondre aux applications choisies tout en s’assurant de la viabilité de leurs implantations. Le budget énergie fixé est un objectif de 100µW. Les applications choisies sont la reconnaissance de posture, la reconnaissance de geste et la capture de mouvement. Les solutions algorithmiques choisis sont une fusion de données de capteurs inertiels par Filtre de Kalman étendu (EKF) et l’ajout d’une classification par analyse en composante principale. La solution retenue pour obtenir des résultats d’implémentation est la synthèse de haut niveau qui permet un développement rapide. Les résultats de l’implantation matérielle sont dominés principalement par l’EKF. À la suite de l’étude, il apparait qu’il est possible avec une technologie 28nm d’atteindre les objectifs de budget énergie pour la partie algorithme. Une évaluation de la gestion haut niveau de tous les composants du nœud est également effectuée afin de donner une estimation plus précise des performances du système dans un cas d’application réel. Une contribution supplémentaire est obtenue avec l’ajout de la détection d’activité qui permet de prédire la charge de calcul nécessaire et d’adapter dynamiquement l’utilisation des ressources de traitement et des capteurs afin d’optimiser l’énergie en fonction de l’activité / Wireless Body Sensor Network (WBSN) is a promising technology that can be used in a lot of application domains from health care to Human Machine Interface (HMI). The BoWI project ambition is to evaluate and design a WBSN that can be used in various applications with daily usage and accessible to the public. This necessitates to design a ultra-low power node that reach a day of use without discomfort for the user. The elected solution is to design a node that operates with the power budget similar to what can be provided by the state of the art of the energy harvesting. An Application Specific Integrated Circuit (ASIC) solution is privileged in order to meet the integration and low power constraints. Designing the dedicated architecture required a preliminary study at several level which are: a state of the art of the energy harvesting in order to determine the objective of energy/power budget of our system, A study of the usage of the system to determine and select typical application cases. A study of the algorithms to address the selected applications while considering the implementation viability of the solutions. The power budget objective is set to 100µW. The application selected are the posture recognition, the gesture recognition and the motion capture. The algorithmic solution proposed are a data-fusion based on an Extended Kalman FIlter (EKF) with the addition of a classification using Principal Component Analysis (PCA). The implementation tool used to design the architecture is an High Level Synthesis (HLS) solution. Implementation results mainly focus on the EKF since this is by far the most power consuming digital part of the system. Using a 28nm technology the power budget objective can be reached for the algorithmic part. A study of the top level management of all components of the node is done in order to estimate performances of the system in real application case. This is possible using an activity detection which dynamically estimates the computing load required and then save a maximum of energy while the node is still.

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

The subject of this master’s thesis was to find the causes of impact toughness scattering of forgings of the test disk with dimension range of 540 – 170 mm. The experimental samples were developed from steel A694 F60. To reach the main aim light microscopy, electron microscopy, EBSD technique, fractographic analysis and hardness measurement HV10 were utilized.

No description available.

An alternative indirect integration regime of porous low-k materials was investigated. Based on a single Damascene structure the intra level dielectric SiO2 or damaged ULK was removed by using HF:H2O solutions to create free standing metal lines. The free spaces between the metal lines were refilled with a spin-on process of a low-k material. The persistence of barrier materials and copper against HF solutions, the gap fill behavior of the used spin on glass on different structure sizes and the main challenges which have to solve in the future are shown in this study.

With the introduction of Internet of Things (IoT) technology in several sectors, wireless, reliable, and energy-saving communication in distributed sensor networks are more important than ever. Thereby, wake-up technologies are becoming increasingly important as they significantly contribute to reducing the energy consumption of wireless sensor nodes. In an indoor environment, the use of wireless sensors, in general, is more challenging due to signal fading and reflections and needs, therefore, to be critically investigated. This paper discusses the performance analysis of wakeup receiver (WuRx) architectures based on two low frequency (LF) amplifier approaches with regard to sensitivity, power consumption, and package error rate (PER). Factors that affect systems were compared and analyzed by analytical modeling, simulation results, and experimental studies with both architectures. The developedWuRx operates in the 868MHz band using on-off-keying (OOK) signals while supporting address detection to wake up only the targeted network node. By using an indoor setup, the signal strength and PER of received signal strength indicator (RSSI) in different rooms and distances were determined to build a wireless sensor network. The results show a wake-up packets (WuPts) detection probability of about 90% for an interior distance of up to 34 m.

No description available.

Thesis (PhD)-- Stellenbosch University, 2013. / ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a better instrument. The largest radio telescope in the world will consist of several arrays, the largest of which, consisting of more than 3000 dishes, will be situated primarily in South Africa. The ambitions of the SKA are grand and their realisation requires technology that does not exist today. Current plans see signals in the band of interest ampli ed, channelised, mixed down and then digitised. An all-digital frontend could simplify receiver structure and improve its performance. Semiconductor (analog-to-digital converters) ADCs continue to make great progress and will likely nd applications in the SKA, but superconductor ADCs bene t from higher clock speeds and quantum accurate quantisation. We propose a superconducting softwarede ned radio frontend. The key component of such a frontend is a superconducting ash ADC. We show that employing such an ADC, even a small- to moderately-sized one, will signi cantly improve the instantaneous bandwidth observable by the SKA, yet retain adequate signal-to-noise ratio so as to achieve a net improvement in sensitivity. This improvement could approach factor 2 when compared to conventional technologies (at least for continuum observations). We analyse key components of such an ADC analytically, numerically and experimentally and conclude that fabrication of such an ADC for SKA purposes is certainly possible and useful. Simultaneously, we address the power requirements of high-performance computing (HPC). HPC on a hitherto unprecedented scale is a necessity for processing the vast raw data output of the SKA. Utilising the ultra-low-energy switching events of superconducting switches (certain Josephson junctions), we develop rst demonstrators of the promising eSFQ logic family, achieving experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the applicability of the eSFQ design concept to arbitrary (unclocked) gates. / AFRIKAANSE OPSOMMING: Supergeleier-elektronika kan 'n beter instrument maak van die \Square Kilometre Array" (SKA). Die wêreld se grootse radioteleskoop sal bestaan uit etlike skikkings, waarvan die grootste - met meer as 3 000 skottels - hoofsaaklik in Suid-Afrika gesetel sal wees. Die SKA is ambisieus en vereis tegnologie wat nog nie vandag bestaan nie. Volgens huidige planne sal seine in die band van belang versterk, gekanalisieer, afgemeng en dan versyfer word. 'n Heel-digitale kopstuk sal die ontvangerstruktuur kan vereenvoudig en sy prestasie kan verbeter. Halfgeleier analoog-na-digital omsetters (ADOs) verbeter voortdurend en sal waarskynlik toepassings in die SKA vind, maar supergeleier ADOs trek voordeel uit hoër klok spoed en kwantumakkurate kwantisering. Ons stel 'n supergeleier sagteware-gede nieerde radio kopstuk voor. Die sleutelkomponent van so 'n kopstuk is 'n supergeleier \ ash" ADO. Ons toon hoe die gebruik van so 'n ADO, selfs een van klein tot matige bisgrootte, die oombliklike bandwydte waarneembaar deur die SKA aansienlik sal verbeter en 'n voldoende sein-tot-ruis verhouding sal behou, en gevolglik 'n netto verbetering in sensitiwiteit sal bereik. Hierdie verbetering kan, vergeleke met konvensionele tegnologie, 'n faktor van 2 nader (ten minste vir kontinuum waarnemings). Ons analiseer belangrike komponente van so 'n ADO analities, numeries and eksperimenteel en lei af dat die vervaardiging van so 'n ADO vir SKA doeleindes beide moontlik en nuttig is. Terselfdertyd spreek ons die drywingsverkwisting van Hoë-verrigting rekenaars aan. Sulke rekenaars van 'n tot dusver ongekende skaal is 'n noodsaaklikheid vir die verwerking van die enorme rou data uitset van die SKA. Deur die gebruik van die ultra-lae-energie skakels van supergeleier skakelaars (sekere Josephson-vlakke), ontwikkel ons die eerste demonstratiewe hekke van die veelbelowende eSFQ logiese familie, en toon eksperimenteel bevestigte skuifregisters en deserieëliseerders met sub-aJ/bis energievereistes. Ons stel verder voor en wys met simulasies hoe om die toepaslikheid van die eSFQ ontwerpkonsep na arbitr^ere (ongeklokte) hekke uit te brei.

Αντικείμενο της διπλωματικής εργασίας είναι η σχεδίαση ενός βιοϊατρικού συστήματος που είναι κατάλληλο για την ανίχνευση εμβοών σε ασθενείς. Το σύστημα αυτό αποτελείται από ένα αναλογικό τμήμα το οποίο περιλαμβάνει τους εξαγωγείς ενέργειας ζώνης συχνοτήτων για τα alpha, gamma και theta waves του εγκεφάλου που τροφοδοτούν τα αντίστοιχα κανάλια του συστήματος. Επίσης, το σύστημα περιλαμβάνει και ένα ψηφιακό τμήμα αποτελούμενο από συγκριτές ρεύματος και μια πύλη AND και το οποίο θα χρησιμεύσει για την λήψη της απόφασης σχετικά με το αν πάσχει ή όχι ο ασθενής. Η έξοδος του συστήματος θα οδηγεί ένα σύστημα ανάδρασης, ο οποίος θα προσαρμόζει τα επίπεδα έντασης των αντίστοιχων σημάτων που δέχεται ο ασθενής για την αποφυγή της εμφάνισης του φαινομένου της εμβοής. Η υλοποίηση του συστήματος γίνεται με χρήση MOS transistors τα οποία λειτουργούν στην περιοχή υποκατωφλίου. Η χρήση μικρών ρευμάτων πόλωσης δίνει τη δυνατότητα για σχεδίαση συστημάτων με χαμηλή κατανάλωση ισχύος και ταυτόχρονα επιτρέπει την υλοποίηση μεγάλων τιμών αντιστάσεων, οι οποίες είναι απαραίτητες για την πραγματοποίηση μεγάλων σταθερών χρόνου που απαιτούνται για τη διαχείριση των χαμηλής συχνότητας βιοϊατρικών σημάτων. Στόχος της διπλωματικής εργασίας είναι η ανάπτυξη πρωτότυπης τοπολογίας για το αναλογικό τμήμα του συστήματος. Αυτό επιτεύχθηκε με την ανάπτυξη νέων δομών φίλτρων τα οποία λειτουργούν στο πεδίο του υπερβολικού ημιτόνου. Οι κύριοι λόγοι υιοθέτησης αυτής της τεχνικής είναι ότι προσφέρει ταυτόχρονα τα παρακάτω: (α) δυνατότητα επεξεργασίας σημάτων τα οποία είναι μεγαλύτερα από το ρεύμα πόλωσης, λόγω της ενσωματωμένης λειτουργίας σε τάξη-ΑΒ, (β) δυνατότητα λειτουργίας με καλή γραμμικότητα σε πολύ χαμηλή τάση τροφοδοσίας, (γ) ηλεκτρονική ρύθμιση των συχνοτικών χαρακτηριστικών τους από το ρεύμα πόλωσης, (δ) υλοποίηση φίλτρων χωρίς αντιστάτες, (ε) υλοποίηση φίλτρων με χρήση μόνο γειωμένων πυκνωτών. Η σχεδίαση των κυκλωμάτων, τόσο σε επίπεδο σχηματικού, όσο και σε επίπεδο μασκών, έγινε με τη χρήση του λογισμικού Cadence και με το Design Kit που παρέχεται από την τεχνολογία AMS CMOS C35 0.35μm. Συγκρινόμενη με την αντίστοιχη ήδη προταθείσα δομή ανιχνευτή εμβοών, η προτεινόμενη τοπολογία προσφέρει τα παρακάτω ελκυστικά χαρακτηριστικά: (α) μειωμένη κατανάλωση ισχύος και (β) λειτουργία του αναλογικού τμήματος σε μικρότερη τάση τροφοδοσίας (0.5V). / Subject of this M. Sc.Τhesis is the design of a biomedical system that is suitable for detecting tinnitus in patients. This system consists of an analog subsystem comprising band energy extractors for alpha, gamma and theta waves of the EEG that feed the channels of the system. The system also includes a digital section composed of current comparator and AND gate, which will serve as a decision on whether or not the suffering patient. The output of the system will drive a feedback system, which will adjust the intensity levels of the respective signals received by the patient to prevent the occurrence of the phenomenon of tinnitus. The system implementation is done using MOS transistors operating in the subthreshold region. The use of low-level bias currents allows for system design with low power consumption and, simultaneously, enables the implementation of large values of resistors that are necessary for the realization of large time constants required for the handling of low frequency biomedical signals. The aim of this thesis is to develop novel topology for the analog subsystem. Tjhis was achieved through the development ddevelopment of novel structures of filters using the concept of filtering in the Sinh-Domain. The main reasons for using this technique is that it simultaneously offers the following attractive characteristics: (a) capability for processing signals which are larger than the bias current, due to the inherent class-AB operation, (b) ability to achieve a relative high linearity at very low power supply voltage, (c) electronic adjustment of frequency characteristics through the bias current, (d) implementation of filters without resistors, and (e) implementation of filters using only grounded capacitors. The design of circuits, both at schematic and post-layout levels was performed using the Cadence software and the Design Kit provided by the AMS CMOS C35 0.35μm technology. Compared with the corresponding already proposed structure tinnitus detector, the proposed topology to offer the following attractive features: (a) reduced power consumption, and (b) operation of the analog section in lower supply voltage (0.5V).

Since their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802.15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868MHz/915MHz/2.4GHz). Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensor node, power consumption of radio frequency front-end (RFFE) must be reduced. To deal with, several approaches are possible, either at circuit level by investigating operating modes of transistors and merging functionalities or at system level by searching novel demodulation architecture. This thesis explores the specific requirements and challenges for the design of ultra-low power radio frequency integrated circuits (RFICs), leading to the design of a compact demodulator implemented in 65 nm CMOS technology and compatible with all modulation schemes.