abstract: The interior of Earth is stratified due to gravity. Therefore, the lateral heterogeneities observed as seismic anomalies by seismologists are extremely interesting: they hold the key to understand the composition, thermal status and evolution of the Earth. This work investigates seismic anomalies inside Earth’s lowermost mantle and focuses on patch-like ultra-low velocity zones (ULVZs) found on Earth’s core-mantle boundary (CMB). Firstly, all previous ULVZ studies are compiled and ULVZ locations on the CMB are digitized. The result is a database, which is publicly available online. A key finding is that there is not a simple mapping between the locations of the observed ULVZs and the large low velocities provinces (LLVPs). Instead, ULVZs are more likely to occur near LLVP boundaries. This spatial correlation study supports a compositionally distinct origin for at least some ULVZs. Next, the seismic structure of the basal mantle beneath the Central America is investigated. This region hosts present and past subducted slabs, which could have brought compositionally distinct oceanic basalt all the way down to the CMB. The waveform distortions of a core-reflected seismic phase and a forward modeling method are used to constrain the causes of the CMB structures. In addition to ULVZ structures, isolated patches of thin zones with shear velocity increased by over 10% relative to background mantle are found for the first time. Ultra-high velocity zones (UHVZs) are interspersed with ULVZs and could be caused by subducted mid-ocean ridge basalt (MORB) that undergoes partial melting and melt segregation. Fe-rich partial melt of MORB can form ULVZs, and silica polymorphs (SiO2) and calcium-perovskite (CaPv) rich solid residue can explain the UHVZs. Finally, large-scale heterogeneities in the lowermost mantle are investigated using S waveform broadening observations. Several basal layer models are case-studied via synthetic calculations. S wave arrivals received at a distance larger than 80˚ in a global dataset from large earthquakes between the years 1994 and 2017 are examined and S waveform broadenings are documented. This approach exploits large distance data for the first time, and therefore is complementary to previous studies in terms of sampling locations. One possible explanation of S waveform broadening is velocity discontinuity inside the D″ layer due to the temperature controlled Bm-pPv phase transition. / Dissertation/Thesis / Doctoral Dissertation Geological Sciences 2020

Les travaux de cette thèse se concentrent sur la réduction de l'énergie consommée et l'amélioration des temps de réveil du microcontrôleur par des innovations au niveau de l'architecture, du circuit et de la gestion de l'énergie. Ces travaux proposent une architecture de microcontrôleur partitionnée entre un processeur de réveil programmable, appelé Wake Up Controller, s'occupant des tâches courantes du nœud de capteurs et un processeur principal gérant les tâches irrégulières. Le Wake Up Controller proposé dans ces travaux de thèse est un processeur RISC 16-bit dont le jeu d'instructions a été adapté pour gérer les tâches régulières du nœud, et n'exécute que du code sur interruptions. Il est implémenté en logique mixte asynchrone/synchrone. Un circuit a été fabriqué en technologie UTBB FDSOI 28nm intégrant le Wake-Up Controller. Le cœur atteint une performance de 11,9 MIPS pour 125μW de consommation moyenne en phase active et un réveil depuis le mode de veille en 55ns pour huit sources de réveil possibles. La consommation statique est d'environ 4μW pour le cœur logique asynchrone à 0,6V sans utilisation de gestion d'alimentation (power gating) et d'environ 500nW avec. / This PhD work focuses on the reduction of energy consumption and wake up time reduction of a WSN node microcontroller through innovations at architectural, circuit and power management level. This work proposes a partitioned microcontroller architecture between a programmable wake up processor, named Wake Up Controller on which this work is focused, and a main processor. The first deals with the common tasks of a wireless sensor node while the second manages the irregular tasks. TheWake Up Controller proposed in this work is a 16-bit RISC processor whose instruction set has been adapted to handle regular tasks of a sensor node. It only executes code on interruptions. It is implemented in asynchronous / synchronous mixed logic to improve wake up time and energy. A circuit was fabricated in a 28nm UTBB FDSOI technology integrating the Wake Up Controller. The core reaches 11,9 MIPS for 125 μW average power consumption in active phase and wakes up from sleep mode in 55ns from eight possible interruption sources. The static power consumption is around 4μW for the asynchronous logic core at 0.6V without power gating and 500nW when gated.

This masters thesis deals with low noise amplifier design for frequency range 1 GHz - 3 GHz. There is a short theoretical introduction in the first part of the thesis. There are described parameters and properties of transistors and general two-ports. Description of the noise characteristics two-ports follows. The next capture contains design of two-stage amplifiers. One of them is with a microstrip filter between stages and the second one is with combline filter on input of the amplifier. The amplifiers and the microstrip filter were designed in program ANSOFT Designer. The design of combline filter was realised in program CST Microwave Studio. Both amplifiers ware made and their properties ware compared with simulations.

Les vibrations ambiantes representent une source potentielle d'energie pour alimentation des capteurs sans fil autonomes. La transduction electrostatique est une des techniques utilisees pour la conversion de l'energie des vibrations en electricite. De nombreuses realisations des transducteurs et leurs circuits de conditionnement ont deja ete presentees dans la litterature. Pour transmettre l'energie convertie vers une charge utile des interfaces specifiques doivent etre concues. Ce dernier sujet a ete peu aborde dans la litterature. Ce travail etudie une interface avec la charge dans un dispositif de recuperation d'energie vibratoire. L'architecture proposee au cours de cette etude est adaptee aux circuits de conditionnement de type pompe de charge, qui fonctionne selon un cycle charge-tension rectangulaire. L'interface proposee accomplit deux taches. Premierement, il permet de transferer l'energie electrique du circuit de conditionnement vers une charge tout en abaissant la tension d'une maniere adiabatique, c.a.d., en minimisant les dissipations. Deuxiemement, il permet de reguler le debit d'extraction d'energie du circuit de conditionnement en ajustant dynamiquement la puissance de ce transfert. Cela est realise avec un circuit integree en technologie 0.35um CMOS haute tension dont l'architecture est inspiree d'un convertisseur DCDC de type Buck fonctionnant en regime discontinu. La consommation de l'interface est minimisee grace a l'utilisation du regime sous le seuil des transistors MOS pour pratiquement tous les blocs, grace a une alimentation reduite a 1.1V. L'interface consomme en dessous de 100nW, et est capable de gerer des sources d'energie a puissance < 1uW. / Vibrational energy is an attractive power source for self-powered wireless sensors. A mainstream harvesting technique for vibrational energy is electrostatic MEMS harvesters. Various circuit architectures have already been introduced with many successful implementation, yet a load interface that efficiently manages the harvested energy has rarely been reported. In this work a load interface is proposed which is suited for any condition circuit (CC) implementing rectangular QV cycles. In general, a rectangular QV conditioning circuit has an optimum interval of which the energy harvested is maximised, thus the harvested energy should be periodically removed to maintain maximising the harvested energy. This is achieved through the load interface (LI). The LI proposed is a switched inductor capacitive architecture with a LI controller allowing the extraction of the energy in a multiple energy shot fashion. The LI controller incorporate an ultra low power clock for switching events and low power comparator for switching decision. Power consumption is reduced by operating at a low supply voltage (1.1V). The LI is implemented in AMS0.35HV technology with a mixed high voltage-low power control blocks. It takes into account the harvester operation to maximise its extracted energy. It overcomes the constrained limited biasing power, tackles resistive losses and power handling transistor long channels by transferring the energy in a multiple shots fashion. A CMOS implementation is proposed along with simulation results showing an average consumed power of the controller less than 100nW allowing the system to operate with input power levels as low as few hundreds of nano-watts.

Carbon dioxide (CO2) is a common working fluid for refrigeration systems. The triple point of CO2 (about −56 °C and 0.51 MPa) is often regarded as the lower operating limit for the con-ventional CO2 vapor compression systems, because below this temperature and pressure, solid CO2 could occur and block the system components. However, if the technical issue could be solved and a stable operation of a vapor compression cycle for heat absorption be-low the triple point pressure (or sublimation cycle) could be realized, there would be a great potential for CO2 to replace the common refrigerants with a very high environmental impact such as R-23 for refrigeration applications below −50 °C. The focus of this work is on the dis-cussion of the feasibly of the sublimation cycle regarding the energy efficiency and the block-ing issues. Seven different two-stage and three-stage CO2 sublimation systems are theoretically evalu-ated and compared to a two-stage R-23 system, which serves as a baseline. A calculation model for the systems is developed. The optimum intermediate pressures for each system as well as the high pressure for the systems in transcritical operations are calculated within the given temperature and pressure constraints. Multiple influence factors, such as the ambient temperature, compressor efficiency, are considered in determining the operating limit and evaluating the performance for each system. In order to find out the cause of the blockages in the sublimation system due to the solid CO2, the solid-gas flow is visualized through experiments. Different throttling devices are investi-gated under various inlet conditions. As the sublimator, a heated sight glass assembly is used. It is found that besides the inlet temperature and pressure condition, the tube wall in the down-stream section of the throttling devices has a great influence on the blockages. A larger heat flux also helps to reduce the blockage in the sublimator. Based on the knowledge gained from the theoretical investigation of the cycle variant and preliminary experiments, a cascade sublimation system is designed, constructed and tested. Despite the fact that the system still requires optimization in terms of energy efficiency and operation stability, it is capable of long continuous operation, and thus the basic feasibility of the sublimation cycle is verified. Finally, the further issues and improvement potentials for the heat transfer and sublimator are discussed.:Acknowledgment Abstract Contents Index of figures Index of tables List of abbreviations and symbols 1 Introduction 1.1 Background and Motivation 1.2 Objective and procedure 2 Fundamentals and state of the art 2.1 The R-744 sublimation cycle 2.2 Expansion into solid-gaseous region and critical flow 2.3 Sublimator and solid-gas two-phase flow 2.4 Summary 3 Thermodynamic analysis of sublimation systems 3.1 Definition of the cycle variants 3.1.1 The baseline system 3.1.2 R-744 cascade systems 3.1.3 R-744 booster systems 3.2 Boundary conditions 3.3 Description of the models 3.3.1 Compressor 3.3.2 Heat exchangers 3.3.3 Other components 3.3.4 Fluid properties 3.4 Process calculation and optimization 3.5 Results and discussion 3.5.1 General boundary conditions 3.5.2 Variable temperatures 3.5.3 Variable compressor efficiency 3.5.4 Variable pressure loss and superheating in the sublimator 3.6 Evaluation of the system variants 4 Experimental visualization of the solid-gas flow 4.1 Throttling below the triple point 4.1.1 Experimental setup - test rig I 4.1.2 Results and discussion 4.2 CO2-Sublimation in a horizontal channel 4.2.1 Experimental setup - test rig II 4.2.2 Results and discussion 4.3 Summary 5 Experimental investigation on the performance of a cascade sublimation system 5.1 Experimental setup – test rig III 5.1.1 The refrigerant cycles 5.1.2 The sublimating unit 5.2 Methodology 5.2.1 The measuring procedure 5.2.2 Data evaluation and uncertainty analysis 5.3 Results and discussion 5.3.1 Transient behavior 5.3.2 System performance 5.3.3 Compressor performance 5.3.4 Long period measurements 5.4 Summary 6 Existing issues and optimization potentials 6.1 Blockage-free operation at low wall temperatures 6.1.1 Supplementary experiment 6.1.2 Outlook 6.2 Heat transfer 6.2.1 Supplementary experiment 6.2.2 Outlook 7 Summary Literature Appendix A. Differential evolution A.1 Basics of differential evolution A.2 Convergence of the results for different system variants Appendix B. Mass flow rate from the capillary tubes B.1 Measurement of the mass flow rate B.2. Comparison of the results with the numerical model and correlations Appendix C. Supplement to the measurements of the test rig III C.1 Exemplary measurement of the R-23 operation C.2. Measurement of the air velocity for the sublimator Appendix D. Supplement to the measurements at low wall temperatures D.1. Calculation of the heat transfer coefficients for the airside D.2. Determination of the local sublimation heat transfer coefficients Publications during the PhD study

Point-of-load (POL) converters are used extensively in IT products. Every piece of the integrated circuit (IC) is powered by a point-of-load (POL) converter, where the proximity of the power supply to the load is very critical in terms of transient performance and efficiency. A compact POL converter with high power density is desired because of current trends toward reducing the size and increasing functionalities of all forms of IT products and portable electronics. To improve the power density, a 3D integrated POL module has been successfully demonstrated at the Center for Power Electronic Systems (CPES) at Virginia Tech. While some challenges still need to be addressed, this research begins by improving the 3D integrated POL module with a reduced DCR for higher efficiency, the vertical module design for a smaller footprint occupation, and the hybrid core structure for non-linear inductance control. Moreover, as an important category of the POL converter, the voltage regulator (VR) serves an important role in powering processors in today's electronics. The multi-core processors are widely used in almost all kinds of CPUs, ranging from the big servers in data centers to the small smartphones in almost everyone's pocket. When powering multiple processor cores, the energy consumption can be reduced dramatically if the supply voltage can be modulated rapidly based on the power demand of each core by dynamic voltage and frequency scaling (DVFS). However, traditional discrete voltage regulators (VRs) are not able to realize the full potential of DVFS since they are not able to modulate the supply voltage fast enough due to their relatively low switching frequency and the high parasitic interconnect impedance between the VRs and the processors. With these discrete VRs, DVFS has only been applied at a coarse timescale, which can scale voltage levels only in tens of microseconds (which is normally called a coarse-grained DVFS). In order to get the full benefit of DVFS, a concept of an integrated voltage regulator (IVR) is proposed to allow fine-grained DVFS to scale voltage levels in less than a microsecond. Significant interest from both academia and industry has been drawn to IVR research. Recently, Intel has implemented two generations of very high frequency IVR. The first generation is implemented in Haswell processors, where air core inductors are integrated in the processor's packaging substrate and placed very closely to the processor die. The air core inductors have very limited ability in confining the high frequency magnetic flux noise generated by the very high switching frequency of 140MHz. In the second generation IVR in Broadwell processors, the inductors are moved away from the processor substrate to the 3DL PCB modules in the motherboard level under the die. Besides computers, small portable electronics such as smartphones are another application that can be greatly helped by IVRs. The smartphone market size is now larger than 400 billion US dollars, and its power consumption is becoming higher and higher as the functionality of smartphones continuously advances. Today's multi-phase VR for smartphone processors is built with a power management integrated circuit (PMIC) with discrete inductors. Today's smartphone VRs operate at 2-8MHz, but the discrete inductor is still bulky, and the VR is not close enough to the processor to support fine-grained DVFS. If the IVR solution can be extended to the smartphone platform, not only can the battery life be greatly improved, but the total power consumption of the smartphone (and associated charging time and charging safety issues) can also be significantly reduced. Intel's IVR may be a viable solution for computing applications, but the air core inductor with un-confined high-frequency magnetic flux would cause very severe problems for smartphones, which have even less of a space budget. This work proposes a three-dimensional (3D) integrated voltage regulator (IVR) structure for smartphone platforms. The proposed 3D IVR will operate with a frequency of tens of MHz. Instead of using an air core, a high-frequency magnetic core without an air gap is applied to confine the very high frequency flux. The inductor is designed with an ultra-low profile and a small footprint to fit the stringent space requirement of smartphones. A major challenge in the development of the very high frequency IVR inductor is to accurately characterize and compare magnetic materials in the tens of MHz frequency range. Despite the many existing works in this area, the reported measured properties of the magnetics are still very limited and indirect. In regards to permeability, although its value at different frequencies is often reported, its saturation property in real DC-biased working conditions still lacks investigation. In terms of loss property, the previous works usually show the equivalent resistance value only, which is usually measured with small-signal excitation from an impedance/network analyzer and is not able to represent the real magnetic core loss under large-signal excitation in working conditions. The lack of magnetic properties in real working conditions in previous works is due to the significant challenges in the magnetic characterization technique at very high frequencies, and it is a major obstacle to accurately designing and testing the IVR inductors. In this research, an advanced core loss measurement method is proposed for very high frequency (tens of MHz) magnetic characterization for the IVR inductor design. The issues of and solutions for the permeability and loss measurement are demonstrated. The LTCC and NEC flake materials are characterized and compared up to 40MHz for IVR application. Based on the characterized material properties, both single-phase and multi-phase integrated inductor are designed, fabricated and experimentally tested in 20MHz buck converters, featuring a simple single-via winding structure, small size, ultra-low profile, ultra-low DCR, high current-handling ability, air-gap-free magnetics, multi-phase integration within one magnetic core, and lateral non-uniform flux distribution. It is found that the magnetic core operates at unusually high core loss density, while it is thermally manageable. The PCB copper can effectively dissipate inductor heat with 3D integration. In addition, new GaN device drivers and magnetic materials are evaluated and demonstrated with the ability to increase the IVR frequency to 30MHz and realize a higher density with a smaller loss. In summary, this research starts with improving the 3D integrated POL module, and then explores the use of the 3D integration technique along with the very high frequency IVR concept to power the smartphone processor. The challenges in a very high frequency magnetic characterization are addressed with a novel core loss measurement method capable of 40MHz loss characterization. The very high frequency multi-phase inductor integrated within one magnetic component is designed and demonstrated for the first time. A 20MHz IVR platform is built and the feasibility of the concept is experimentally verified. Finally, new GaN device drivers and magnetic materials are evaluated and demonstrated with the ability to increase the IVR frequency to 30MHz and realize higher density with smaller loss. / Ph. D.

O estudo do comportamento de um perfil de uma seção aerolástica típica, com Reynolds na faixa de microaeronaves, constitui o principal foco deste trabalho, tomando como objetivo a estimativa de parâmetros do fenômeno de flutter. A pesquisa analisa o escoamento de um fluido sobre um corpo (cilindro e perfil de aerofólio) em estado estacionário e oscilante, em escoamento de velocidade constante, e, especificamente, o fenômeno de flutter. As equações de Navier-Stokes, com termo de força, são resolvidas pelo método da fronteira virtual para modelagem da interface escoamento/estrutura, representada pela geometria de um corpo de geometria complexa. Na discretização das equações governantes foi utilizado o método de diferenças finitas, sobre malhas deslocadas, com avanço temporal das velocidades do escoamento por meio de um esquema de Runge-Kutta de ordem 4. Os códigos computacionais, para as simulações das diretrizes e a lógica de cálculo, foram criados no contexto deste trabalho. A verificação foi feita através do método da solução manufaturada por meio de um problema fictício, que tem uma solução analítica conhecida, e que preenche as condições de contorno implementadas no código. O modelo da fronteira virtual é testado para os casos de escoamento sobre cilindro de base quadrada, cilindro de base circular e perfil de aerofólio tipo NACA0012, com malhas regular e não regular, e para condições estacionária e sob oscilação forçada. Foi estudado o comportamento de formação de vórtices, provocados por escoamento uniforme sobre o perfil de aerofólio, através dos coeficientes de arrasto, sustentação e pressão com visualização por meio da vorticidade e linhas de corrente, para vários ângulos de ataque e oscilação forçada com elevação e rotação em torno de um pivô posicionado no centro geométrico do perfil (50% da corda). Finalmente, é apresentada uma determinação numérica das características aeroelásticas para o perfil de aerofólio NACA0012, em escoamento de número de Reynolds ultra baixo (Re = 1.000), e parâmetros de flutter para um caso de baixa frequência de oscilação. / The behavior study of a profile of a typical aerolastic section, with Reynolds in range of micro aerial vehicle, is the main focus of this work, taking as objective the estimation of parameters of flutter phenomenon. The research analyzes of the flow of a incompressible fluid on a body (cylinder and airfoil profile) at steady state and oscillating with constant speed and, specifically, the flutter phenomenon. The Navier-Stokes equations, with force term, are solved by virtual boundary method for modeling interface flow/structure, represented by the geometry of a body of complex geometry. In discretization of the governing equations, the method of finite differences on staggered grid, with temporal advancement of discharge velocity through a Runge-Kutta of order 4. The computer codes, for simulations guidelines and logic calculation, were created in the context of this work. The verification was done by method ofmanufactured solution through a fictional problem, which has a known analytical solution, and satisfies the boundary conditions implemented in code. The model of the virtual boundary is tested for cases of flow over a square cylinder, circular cylinder and profile of a NACA0012 airfoil type, with regular and non-regular meshes, over stationary and forced oscillation conditions. We studied the behavior of vortex formation, caused by uniform flow over the airfoil profile, by the drag, lift and pressure coefficients with view through the vorticity and streamlines for various attack angles and forced oscillation with plunge and pich around a pivot witch was positioned at the geometric airfoil profile (half chord). Finally, it is presented a numerical determination of aeroelastic characteristics for the NACA0012 airfoil profile, flow under ultra low Reynolds number, and flutter parameters for a case of low oscillation frequency.

Foram realizados ensaios tribológicos de deslizamento do par Si3N4-Al2O3, lubrificado com água, na configuração esfera contra disco, sendo a esfera de nitreto de silício e o disco de alumina para investigar a influência da velocidade de deslizamento, da carga aplicada e da temperatura no coeficiente de atrito. As esferas de nitreto de silício e os discos de alumina foram caracterizados determinando-se: densidades, dureza Vickers, módulo de elasticidade e tenacidade à fratura. Os ensaios foram realizados com rugosidade inicial nos discos de Rrms = 352 nm. O regime de ultra baixo coeficiente de atrito (UBCA, &#956; < 0,01) foi atingido após um período de running-in de aproximadamente uma hora e o coeficiente de atrito ficou na faixa de &#956; = 0,008 a &#956; = 0,002. Os resultados mostraram que este sistema deslizante tem características hidrodinâmicas, pois o coeficiente de atrito diminuiu com o aumento da velocidade de deslizamento. Uma variação suave da carga aplicada fez com que o coeficiente de atrito permanecesse no regime de UBCA, com a carga aplicada variando de 54 N até 94 N. Em temperaturas menores ou iguais a 11°C o sistema não atingiu o regime de UBCA e o coeficiente de atrito final ficou da ordem de centésimos. Foi observado o fenômeno de UBCA em temperaturas de 30 e 40°C. No entanto, nestas temperaturas, a baixa viscosidade da água não deveria permitir que o sistema atingisse o regime de UBCA. A análise dos dados possibilitou inferir que durante o regime de UBCA o sistema desliza num regime de lubrificação mista, sendo lubrificação hidrodinâmica, devido ao filme de água, somada a lubrificação limite, devido às camadas hidratadas formadas nas superfícies das cerâmicas. Os resultados mostraram que a temperatura influencia no desgaste das cerâmicas. A determinação do volume desgastado possibilitou observar que durante os ensaios a alumina sofre menos desgaste que o nitreto de silício e que o desgaste de ambas cerâmicas aumenta com o aumento da temperatura. / Tribological tests were conducted in a ball on disk setup, using water as lubricant. Were used a silicon nitride ball and alumina disk. The tests were conducted to investigate the effects of sliding speed, applied load and temperature on friction coefficient. The silicon nitride balls and alumina disks were characterized by determining density, Vickers hardness, elastic modulus and fracture toughness. The tests were conducted with initial roughness on the disk surface of 352 nm. The ultra low friction coefficient regime (ULFC, &#956; < 0.01) was reached after a running-in period of approximately one hour and the friction coefficient remains in the range of &#956; = 0.008 a &#956; = 0.002 during this steady state regime. The results showed that this sliding system has hydrodynamic characteristics, because the friction coefficient decreased with increasing of the sliding speed. With an smooth variation of the applied load the system remained in the ULFC regime, when the applied load varied from 54 N up to 94 N. At temperatures below or equal to 11°C the system did not reach the ULFC regime and the final friction coefficient was the order of hundredths. We observed the ULFC phenomenon at temperatures of 30 and 40°C. However, at these temperatures, the water viscosity is low and should not allow the system to reach the ULFC regime. The data analysis allowed infer that during the ULFC regime the system slides with a mixed lubrication regime, hydrodynamic plus limitrofe, the first due to water film and the second due to the hydrated layer formed on the ceramics surfaces. The results showed a influences of temperature in the ceramics wear. The results of the worn volume allowed to observe that during the tests alumina suffers less wear than the silicon nitride, and the ceramics wear increases with increasing temperature.

Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap. / A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

Les capteurs sans fil ont un avenir prometteur c’est pourquoi leur développement est àl’origine de nombreuses recherches. Leur autonomie reste cependant un problème à résoudre.Les travaux de cette thèse se concentrent précisément sur cette problématique : trouverune stratégie permettant aux capteurs d’être autonomes en énergie.L’énergie nécessaire à l’alimentation du capteur, quel que soit son mode de fonctionnement,doit en effet être récupérée de l’environnement dans lequel le capteur se trouve. Deplus, en cas d’absence ou d’insuffisance d’énergie environnante, le fonctionnement du capteurdoit pouvoir perdurer. À cela s’ajoute la nécessité de connaitre à tout instant la quantitéd’énergie disponible afin de pouvoir maintenir un niveau de charge constant et ainsi prolongerla vie du capteur. Enfin, toute cette gestion de l’énergie doit pouvoir garantir le meilleurrendement possible.Cette étude a conduit à la conception et au test d’un circuit en technologie CMOS 90nm.Ce même circuit a été intégré dans les capteurs sans fil d’un réseau en cours de développement.Et enfin, une méthode permettant de connaitre le niveau d’énergie embarquée a étémise au point et pourra permettre à l’avenir la conception d’un nouveau circuit de power managementpour capteurs autonomes en énergie. / Wireless sensors have a bright future so their development is causing a lot of research.However, their autonomy is still an issue.This work focuses on this problem : find a strategy for the sensors to be autonomous.The energy required to power the sensor, whatever its working mode, must indeed be harvestedfrom the environment wherein the sensor is located. Moreover, in case of absence ora lack of available energy, the sensor has to keep working. Additionnaly the state-of-chargehas to be known in real time in order to extend the sensor lifetime. Finally, the energy managementhas to give the highest efficiency.This study led to the design and the test of a circuit in CMOS 90nm technology. Thiscircuit was integrated in wireless sensors for networks under development. Finally, a methodto estimate the level of energy in the sensor has been developed and will allow to design anew circuit of power management for wireless sensor network.