<p>I detta examensarbete har olika sätt att implementera färgrymdskonverterare i multipel konstant multiplikationsteknik beskrivits med VHDL, syntetiserats och jämförts med avseende på effektförbrukning.</p>

En del av en Audioanalystor har blivit utveckladoch implementerad som en applikation i det hårdvarubeskrivande språket VHDL. Denna del har sedan programmerats in i en PLD-krets på ett kretskort som används i audiotester för mobiltelefoner på Flextronics. Applikationen konverterar data så att det ska gå att skicka information mellan telefonen och olika mätinstrument. Applikationen består av två äldre applikationer. Av dessa två har en blivit helt implementerad. I den andra kvarstår att finna orsaken till varför den ger ifrån sig felaktigt data i form av oönskat brus. Arbetet avbröts p.g.a. slutdatum. A part of an audio analyzer has been developed and implemented as an application in the hardware description language VHDL. This part has later been programmed into a PLD device on a circuit board used for audio tests on mobile telephones at Flextronics. The application converts data, making it possible to send information between the telephone and different measuring instruments. The application consists of two older applications. One of them has been fully implemented. What is left in the other part is to find the cause why it is sending wrong data as unwanted noise. The work had to be stopped when deadline was reached / A part of an audio analyzer has been developed and implemented as an application in the hardware description language VHDL. This part has later been programmed into a PLD device on a circuit board used for audio tests on mobile telephones at Flextronics. The application converts data, making it possible to send information between the telephone and different measuring instruments. The application consists of two older applications. One of them has been fully implemented. What is left in the other part is to find the cause why it is sending wrong data as unwanted noise. The work had to be stopped when deadline was reached.

This thesis is investigating the new globally asynchronous locally synchronous (GALS) technology for integrated circuits. Different types of asynchronous wrappers are tested and a new wrapper design is presented. It also investigates the possibility to use VHDL for asynchronous simulation and synthesis. The conclusions are that the GALS technology is possible to use but that it needs new synthesis tools, because todays tools are designed for synchronous technology.

The purpose of this thesis is to explore the formal verification technique of completion functions and equivalence checking by verifying two pipelined cryptographic circuits, KASUMI and WG ciphers. Most of current methods of communications either involve a personal computer or a mobile phone. To ensure that the information is exchanged in a secure manner, encryption circuits are used to transform the information into an unintelligible form. To be highly secure, this type of circuits is generally designed such that it is hard to analyze. Due to this fact, it becomes hard to locate a design error in the verification of cryptographic circuits. Therefore, cryptographic circuits pose significant challenges in the area of formal verification. Formal verification use mathematics to formulate correctness criteria of designs, to develop mathematical models of designs, and to verify designs against their correctness criteria. The results of this work can extend the existing collection of verification methods as well as benefiting the area of cryptography. In this thesis, we implemented the KASUMI cipher in VHDL, and we applied the optimization technique of pipelining to create three additional implementations of KASUMI. We verified the three pipelined implementations of KASUMI with completion functions and equivalence checking. During the verification of KASUMI, we developed a methodology to handle the completion functions efficiently based on VHDL generic parameters. We implemented the WG cipher in VHDL, and we applied the optimization techniques of pipelining and hardware re-use to create an optimized implementation of WG. We verified the optimized implementation of WG with completion functions and equivalence checking. During the verification of WG, we developed the methodology of ``skipping" that can decrease the number of verification obligations required to verify the correctness of a circuit. During the verification of WG, we developed a way of applying the completion functions approach such that it can deal with a circuit that has been optimized with hardware re-use.

Allting började med att jag fick i uppdrag av Euromaint Industry i Skövde att konstruera en alfanumerisk display i syfte att ersätta en utgången display som inte längre nytillverkas. Jag fick i uppdrag att välja ut en modern, lämplig grafisk display och bygga ett interface mellan den nya displayen och den industriella maskin som displayen skall sitta på. Efter att ha letat hos någraelektronikleverantörer kom jag fram till att en TFT-skärm från det japanska företaget Kyocera var den som passade bäst. Skärmen hade ett VGA-liknandeinterface och min uppgift blev att sätta mig in i hur VGA fungerar. Efter att ha konstaterat att det krävdes en snabbare krets än en microcontroller för att använda VGA, var det endast en programmerbar logikkrets, en FPGA, som gällde. Denna FPGA sköter nu ensam om såväl VGA-interfacet som inläsningen av informationen från den industriella NC-maskinen. / Everything started when I got a task from Euromaint Industry in Skövde, Sweden, to develop an alphanumerical display that could replace an old one, which was sold out. I got a task to choose a modern, suitable, graphical display and develop an interface between the new display and the industrial machine, which the old one was connected to. I have searched for a display at some suppliers of electronic components and I have found a TFT-display from the Japanese company Kyocera. The display had an interface similar to VGA so I had to study VGA to see how it works. Then I realized that I needed a faster circuit than a microcontroller. Then I chose a programmable logic circuit, an FPGA, to control the VGA-sweep. Today the FPGA-circuit controls the whole system.

AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.

The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with RocketTMIO GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz. / Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.

Detta examensarbete har som syfte att konstruera en prototyp av en testsändare inom Sbandet,2.2 – 2.4 GHz. Arbetet innefattar konstruktion och utveckling av hårdvara och kodför testsändaren, samt tester och optimering av den framtagna prototypen.Koden designades för en FPGA i Quartus II med VHDL. I FPGA:n hanteraskommunikationen mellan användaren och hårdvaran. Designen av mönsterkortet gjordes iprogrammet Altium Designer. Det resulterade i ett kretskort i glasfiber med två lager ochytmonterade komponenter som handlöddes. Huvudkretsarna i hårdvaran är en FPGA, enfrekvensmixer, en lokaloscillator och två olika förstärkare. Lokaloscillatorn genererarbärfrekvensen medans FPGA:n modulerar indata och omvandlar det till datafrekvenser.Mixern blandar bärfrekvensen med data via amplitudmodulering och ger ut en RF-signalsom förstärks innan den sänds ut.Resultatet efter optimering är att testsändaren genererar en ren bärfrekvens inomS-bandet och kompenserar väl för modulationsfel vid generering av RF-signalen. Denöverför data som vid test kan avläsas och valideras av en demoduleringsapparat förflygdata.

Avionics Division of Saab AB develops advanced electronics that need to be robust and work in harsh environments with for example extreme temperatures and cosmic radiation without any failure. To succeed with this the electronics need to be simulated and tested. Therefore this thesis work is done to strengthen the Avionics Division’s knowledge of hardware modelling and simulation by evaluating the simulation tools LTSpice, PSpice and SystemVision, their functions and capabilities. In this thesis a survey is carried out with help of a questionnaire to study the Avionics Division’s needs for simulation. The survey is underlying an analysis of the analyses that can be performed by the simulation tools for example Sensitivity analysis, Worst Case analysis, Monte Carlo analysis and Parametric Sweep analysis. The different analyses are discussed in the thesis. The questionnaire is also underlying an analysis of the tools LTSpice, PSpice and SystemVision. The result of the analysis is summarized in Table 1. A case study of a circuit simulation in SystemVision, based on an existing circuit used by Avionics Division, is also done within this thesis work. The study is done to evaluate the tool’s usability, to see if it is easy to perform a simulation and if it is easy to find and use suitable models from the model library. The case study describes how a simulation is performed in SystemVision and how an AC analysis of a Butterworth filter is done. A stability and reliability check of the tool is performed as well as a robustness simulation. The analyses were easy to do and the overall impression is that SystemVision is reliable and user friendly structured. In order to check and compare the results of the AC analysis the same analysis is performed using LTSpice. The comparison shows that the results differ. This depending on that the models of the circuit were some what different in LTSpice and SystemVision. The final conclusion is that SystemVision would fit within Avionics Division’s workflow. Using SystemVision demands education of the engineers to secure maximum use of all the advantages of SystemVision.

In this thesis a number of energy saving methods for a multiplier on algorithmic level are investigated. For the investigation a multiplier is constructed in VHDL, after which the circuit's performance is investigated. A number of techniques for reduced power consumption are introduced in the circuit and are then evaluated. The conclusions are that all investigated methods, pipelining, interleaving and voltage scaling, should be maximally made use of in order to minimize the power consumption. / I detta arbete undersöks ettantal energibesparande metoder för en multiplikator på algoritmnivå. För undersökningen konstrueras en multiplikator i VHDL, varefter kretsens prestanda undersöks. Ett antal tekniker för minskad effektförbrukning införs i kretsen och utvärderas därefter. Slutsatsen är att samtliga undersökta metoder, pipelining, interleaving och spänningsskalning, bör utnyttjas maximalt för att minimera effektförbrukningen.