Increasingly, soft processors are being considered for use within FPGA-based reliable computing systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including single event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xilinx Radiation Test Consortium's (XRTC's) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA's configuration memory. This tool was used to show that the sensitivity of the configuration memory of a soft processor depends on several variables, including its microarchitecture, its customizations and features, and the software instructions that are executed. The fault injection experiments described in this thesis were performed on five different soft processors, i.e., MicroBlaze, LEON3, Arm Cortex-M0 DesignStart, OpenRISC 1200, and PicoBlaze. Emphasis was placed on characterizing the sensitivity of the MicroBlaze soft processor and the dependence of the sensitivity on various modifications. Seven benchmarks were executed through the various experiments and used to determine the SEU sensitivity of the soft processor's configuration memory to the instructions that were executed. In this thesis, a wide variety of soft processor fault injection results are presented to show the differences in sensitivity between multiple soft processors and the software they run.

Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar processing system must also be small and efficient.This thesis presents the design of the processing system for a small Frequency Modulated Continuous Wave (FMCW) phased array radar. The radar and processing is designed to be light-weight and low-power in order to fly onboard a UAV less than 25 kg in weight. The radar algorithms for this design include a parallelized Fast Fourier Transform (FFT), cross correlation, and beamforming. Target detection algorithms are also implemented. All of the computation is performed in real-time on a Xilinx Zynq 7010 System on Chip (SoC) processor utilizing both FPGA and CPU resources.The radar system (excluding antennas) has dimensions of 2.25 x 4 x 1.5 in3, weighs 120 g, and consumes 8 W of power of which the processing system occupies 2.6 W. The processing system performs over 652 million arithmetic operations per second and is capable of performing the full processing in real-time. The radar has also been tested in several scenarios both airborne on small UAVs as well as on the ground. Small UAVs have been detected to ranges of 350 m and larger aircraft up to 800 m. This thesis will describe the radar design architecture, the custom designed radar hardware, the FPGA based processing implementations, and conclude with an evaluation of the system's effectiveness and performance.

A ferramenta ChipCflow vem sendo desenvolvida nos últimos quatro anos, inicialmente a partir de um projeto de arquitetura a fluxo de dados dinâmico em hardware reconfigurável, mas agora como uma ferramenta de compilação. Ela tem como objetivo a execução de algoritmos por meio do modelo de arquitetura a fluxo de dados associado ao conceito de dispositivos parcialmente reconfiguráveis. Sua característica principal é acelerar o tempo de execução de programas escritos em Linguagem de Programação de Alto Nível (LPAN), do inglês, High Level Languages, em particular nas partes mais intensas de processamento. Isso é feito por meio da implementação dessas partes de código diretamente em hardware reconfigurável - utilizando a tecnologia Field-programmable Gate Array (FPGA) - aproveitando ao máximo o paralelismo considerado natural do modelo a fluxo de dados e as características do hardware parcialmente reconfigurável. Neste trabalho, o objetivo é a prova de conceito do processo de partição e do protocolo de comunicação entre as partições definidas a partir de um Grafo de Fluxo de Dados (GFD), para a execução direta em hardware reconfigurável utilizando Reconfiguração Parcial Dinâmica (RPD). Foi necessário elaborar um mecanismo de partição e protocolo de comunicação entre essas partições, uma vez que a RPD insere características tecnológicas limitantes não encontradas em hardwares reconfiguráveis mais tradicionais. O mecanismo criado se mostrou parcialmente adequado à prova de conceito, significando a possibilidade de se executar GFDs na plataforma parcialmente reconfigurável. Todavia, os tempos de reconfiguração inviabilizaram a proposta inicial de se utilizar RPD para diminuir o tempo de tag matching dos GFDs dinâmicos / The ChipCflow tool has been developed over the last four years, initially from an architectural design the flow of Dynamic Data in reconfigurable hardware, but now as a compilation tool. It aims to run algorithms using the model of the data flow architecture associated with the concept of partially reconfigurable devices. Its main feature is to accelerate the execution time of programs written in High Level Languages, particularly in the most intense processing. This is done by implementing those parts of code directly in reconfigurable hardware - using FPGA technology - leveraging the natural parallelism of the data flow model and characteristics of the partially reconfigurable hardware. In this work, the main goal is the proof of concept of the partition process and protocol communication between the partitions defined from Data Flow Graph for direct execution in reconfigurable hardware using Active Partial Reconfiguration. This required a mechanism to partition and a protocol for communication between these partitions, since the Active Partial Reconfiguration inserts technological features limiting not found in traditional reconfigurable hardware. The mechanism developed is show to be partially adequate to the proof of concept, meaning the ability to run Data Flow Graphs in a platform that is partially reconfigurable. However, the reconfiguration time inserts a great overhead into the execution time, which made the proposal of the use of Active Partial Reconfiguration to decrease the time matching Data Flow Graph unfeasible

A VHDL evaluation platform and interface to the Xilinx Aurora 8b/10b IP has been designed, tested and evaluated. The evaluation platform takes an arbitrary amount of data sources and sends the data over 1,2,4 or 8 multi gigabit serial lanes, using the Aurora 8b/10b protocol. A lightweight communications protocol for point-to-point data transfer, error detection and recovery is used to maintain a reliable and efficient transmission scheme. Priority between sources sharing the serial link is also a part of the platform. The Aurora 8b/10b IP is a lightweight protocol and transceiver interface for Xilinx FPGAs, based on the 8b/10b line encoding protocol. In addition, a demonstration PCB has been developed to introduce the Kintex-7 FPGA to future products at SAAB Dynamics.

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results. / I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.

Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.

Tato diplomová práce se zabývá návrhem sekvenčních digitálních obvodů s ohledem na optimalizaci zpoždění. V práci je popsána problematika dvou technik, které jsou běžně používané při optimalizaci – stručně je popsána technika tzv. synchronizace registrů (angl. retiming), větší pozornost je však věnována technice tzv. zřetězení (angl. pipelining). V rámci praktické části byla vypracována forma abstrakce sekvenčních digitálních obvodů pomocí acyklických orientovaných grafů. Obvod je tak přenesen do roviny, ve které je jednodušší jej transformovat. Zároveň je představen nástroj pro polo-automatickou optimalizaci digitálních obvodů vyvíjených v prostředí Xilinx ISE Design Suite využitím techniky zřetězení.

Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.

This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.

This work deals with the design and implementation of high-speed communication interfaces into FPGA chip and their utilizing for image transmission and processing. In the implementation part has been created PCI Express endpoint device, which provides data transfers between the FPGA chip and computer RAM memory. As a source of image data for further processing was connected the Unicam M621 camera throught the Ethernet interface to FPGA chip. The project was implemented on the Xilinx SP605 development board. Using both of the the interfaces were demonstrated on the application of edge detection using Sobel operator. The PCI Express endpoint device driver for the Linux operating system and a simple application interface in C language was also created within this project.