In this thesis, we discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance, and the data (information bit) rate. In order to decrease the latency a parallelized decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantization scheme and normalization approximations, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

<p>Ett digitalt vågfilter av Richardstyp har implementerats i en FPGA på ett utvecklingskort. Sampel kan skickas till filtret och mottas från filtret via serieporten på en dator. Metoden som användes är att en modell av filtret konstruerades i Simulink. Filtret har modifierats med avseende på skalning, brus och stabilitet. VHDL-koden till filtret genererades i Simulink genom att bygga modellen av Xilinx Blockset. Ytterligare VHDL-kod konstruerades för att kunna skicka sampel mellan filter och minnet på utvecklingskortet. För kommunikation mellan minnet på utvecklingskortet och dator utnyttjades färdiga lösningar.</p> / <p>Filtrets funktion efter implementeringen var samma som modellens byggd i Simulink. A Richards’ structure wave digital filter has been implemented on an evaluation board in an FPGA. Samples can be sent to the filter and received from the filter using the serial port of a computer. The method used is that a modell of the filter has been created in Simulink. The filter has been modified with respect to scaling, noise and stability. VHDL for the filter has been generated in Simulink by using Xilinx blockset to build the modell. Also, VHDL has been constructed to be able to send samples between the filter and the memory on the evaluationboard. For communication between the memory on the evaluationboard and the computer, existing solutions have been used. The functionality of the filter after implementation was the same as in the modell built in Simulink.</p>

In this thesis a microcontroller core is developed in an FPGA. Its instruction set is compatible with the microcontroller PIC16XX series by Microchip Technology. The microcontroller employs a RISC architecture with separate busses for instructions and data. Our goal in this research is to implement and evaluate the design in the FPGA. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can lead to designs containing millions of logic gates, memories, high-speed interfaces, and other high-performance components. In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize FPGAs in many designs. A test demo board from the Digilent Inc is used to fit our testing requirements of the RISC microcontroller. The test demo board also had the capability of communicating with a personal computer (PC) so that we can load the program from PC. Based on the modern design methods the microcontroller core is developed using the Verilog hardware description language. Xilinx ISE Foundation 6.3i software is used for its synthesis and implementation. An embedded test program code using MPLAB is also developed, and then loaded into the designed microcontroller residing in the FPGA. In order to perform a functional test of the microcontroller core a special test program downloader application is designed by using Borland C++ Builder. First, the specification from the PIC16XX datasheet is transferred into an abstract behavioral description. Based on that, the next step is to develop a description of the microcontroller core with some minor modifications which can be synthesizable into a FPGA. Finally, the resulting gate level netlist is evaluated and tested using a demo board.

Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part. High performance of the processor is always desirable, so there is an interest in finding faster solutions.This report aims to describe the work and results performed by Karl Bengtson and Olof Andersson at ISY. The task was to continue the development of a soft core microprocessor, originally created by Andreas Ehliar. The first step was to decide a more widely adopted instruction set for the processor. The choice fell upon the MIPS32 instruction set. The main work of the project has been focused on implementing support for MIPS32, allowing the processor to execute MIPS assembly language programs. The development has been done with speed optimization in mind. For every new function, the effects on the maximum frequency has been considered, and solutions not satisfying the speed requirements has been abandoned or revised.The performance has been measured by running a benchmark program—Coremark. Comparison has also been made to the main competitors among soft core processors. The results were positive, and reported a higher Coremark score than the other processors inthe study. The processor described herein still lacks many essential features. Nevertheless, the conclusion is that it may be possible to create a competitive alternative to established soft processors. / FPGAer används idag ofta för stora inbyggda system, i vilka en mjuk processor ofta spelar en viktig roll. Hög prestanda hos processorn är alltid önskvärt, så det finns ett intresse i att hitta snabbare lösningar. Denna rapport skall beskriva det arbete och de resultat som uppnåtts av Karl Bengtson och Olof Andersson på ISY. Uppgiften var att fortsätta utvecklandet av en mjuk processor, som ursprungligen skapats av Andreas Ehliar. Första steget var att välja ut en mer allmänt använd instruktionsuppsättning för processorn. Valet föll på instruktionsuppsättningsarkitekturen MIPS32. Projektets huvutarbete har varit fokuserat på att implementera stöd för MIPS32, vilket ger processorn möjlighet att köra assemblerprogram för MIPS.Utvecklingen har gjorts med hastighetsoptimering i beaktning. För varje ny funktion har dess effekter på maxfrekvensen undersökts,och lösningar som inte uppfyllt hastighetskraven har förkastats eller reviderats. Prestandan har mätts med programmet Coremark. Det har också gjorts jämförelser med huvudkonkurrenterna bland mjuka processorer. Resultaten var positiva, och rapporterade ett högre Coremarkpoäng än de andra processorerna i studien. Slutsatsen är att det ärmöjligt att skapa ett alternativ till de etablerade mjuka processorerna, men att denna processor fortfarande saknar väsentliga funktioner som behövs för att utgöra en mogen produkt.

PANDA is the next generation hadron physics detector under construction at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt, Germany to accurately detect and parameterize particles with kinetic energies from 1MeV to 8GeV. PANDA is a 4π detector and due to its unique shape, all the readout electronic from ADC modules, power supplies, and a controller unit is housed in the liquid-cooled crates mounted inside the detector. Therefore, the readout electronics are exposed to a high level of magnetic field and radiation. The controller unit as the critical component of the digitization system with adequate radiation resiliency governs the crate. The control unit manages power supplies, monitors the radiation damages of each ADC modules, offer a mechanism to re-program the ADC module firmware, and finally features a redundant communication for the crate over fiber optics. The purpose of this thesis is to study and design the controller unit hardware that meets the specification of the PANDA experiment.

High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless compression algorithms and the implementation operate at 214.3 MHz with a max throughput of 3.43 Gbit/s. The compression ratio is compared to that of competing implementations from Teledyne DALSA Inc. and Pleora Technologies on a set of typical 3D range data images. The proposed algorithm achieve a higher compression ratio while maintaining a small hardware footprint.

Master thesis is dealing with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In theoretical part of thesis are explained different types of mechanism used for providing quality of service in communication networks. Furthermore the brief description o VHDL, FPGA and framework Netcope Development Kit is a piece of theoretical part as well. The outcome of practical part contains a design, limiting packet queues based on Tocken Bucket mechanism. Design verification was made by simulations, synthesis and real implementation on smart NIC NFB-200G2QL. All kind of verificaion results are summerized in last three chapters.

In this work I describe digital predistortion in baseband used for amplifier linearization. Non-linearity is one of the worst disadvantages of Power amplifiers and decreasing of its is useful from many reasons. Work examines system which contains: Data source, which is represented by QPSK or OFDM modulator, predistorter, Power amplifier (model of non-linearity) and unit used to update coeficients for predistorter adaptation. System is simulated in MATLAB and Xilinx (simulation by ModelSim). Results are compared, described and commented.

This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.

Die vorliegende Diplomarbeit untersucht die Verdrahtungsressourcen von Xilinx-FPGAs, indem das LCA-Format der 4000er Familie beschrieben und ein Lösungsansatz für das Verdrahtungsproblem präsentiert wird. Bei der Untersuchung des LCA-Formats war die Arbeit mit dem XACT-Design-Editor xde, der ebenfalls Dateien im LCA-Format als Eingabe- und Ausgabedateien nutzt, sehr wichtig. Die Beschreibung ist zwar auf den Baustein XC4002A bezogen, aber sie gilt für alle 4000er Bausteine, weil die Bausteine dieser Familie dieselben Elemente besitzt aber mit verschiedener Anzahl. Um sicher zu sein, daß die Beschreibung des LCA-Formats exakt ist, wurde das LCA-File für einen Volladdierer manuell hergestellt und mit dem LCA-File, der durch das Programm PPR von Xilinx