For applications such as live video processing, there is a high demand for high performance and low latency solutions. The configurable logic in FPGAs allows for custom hardware to be tailored to a specific video application. These FPGA designs require technical expertise and lengthy implementation times by vendor tools for each unique solution. This thesis presents a dynamically configurable topology as an FPGA overlay to deploy custom hardware processing pipelines during run-time by utilizing dynamic partial reconfiguration. Within the FPGA overlay, a configurable topology with a routable switch allows video streams to be copied and mixed to create complex data paths. This work demonstrates a dynamic video processing pipeline with 11 reconfigurable regions and 16 unique processing cores, allowing for billions of custom run-time configurations.

Vestavený hardware je velice populární v této době. Proto jsme se rozhodli vytvořit desku s mikrokontrolérem AT91SAM9261 spolu so standartným a nestandartným hardwarem. Standartným, běžným by se dal nazvat port LAN alebo audio vstup-výstup. Nestandartným, špecialním by mohl být obvod FPGA firmy Xilinx o velikosti 200k. Toto dovoluje využít zažízení v oblastech, kde výpočetní síla obyčejnýho CPU již není dostačující.

The field-programmable gate array (FPGA) is a dynamically reconfigurable digital logic chip used to implement custom hardware. The large densities of modern FPGAs and the capability of the on-thely reconfiguration has made the FPGA a viable alternative to fixed logic hardware chips such as the ASIC. In high-performance computing, FPGAs are used as co-processors to speed up computationally intensive processes or as autonomous systems that realize a complete hardware application. However, due to the limited capacity of FPGA logic resources, denser FPGAs must be purchased if more logic resources are required to realize all the functions of a complex application. Alternatively, partial reconfiguration (PR) can be used to swap, on demand, idle components of the application with active components. This research uses PR to swap components to improve the performance of the application given the limited logic resources available with smaller but economical FPGAs. The swap is called ”resource sharing PR”. In a pipelined design of multiple hardware modules (pipeline stages), resource sharing PR is a technique that uses PR to improve the performance of pipeline bottlenecks. This is done by reconfiguring other pipeline stages, typically those that are idle waiting for data from a bottleneck, into an additional parallel bottleneck module. The target pipeline of this research is a two-stage “slow-toast” pipeline where the flow of data traversing the pipeline transitions from a relatively slow, bottleneck stage to a fast stage. A two stage pipeline that combines FPGA-based hardware implementations of well-known Bioinformatics search algorithms, the X! Tandem algorithm and the Smith-Waterman algorithm, is implemented for this research; the implemented pipeline demonstrates that characteristics of these algorithm. The experimental results show that, in a database of unknown peptide spectra, when matching spectra with 388 peaks or greater, performing resource sharing PR to instantiate a parallel X! Tandem module is worth the cost for PR. In addition, from timings gathered during experiments, a general formula was derived for determining the value of performing PR upon a fast module.

This thesis presents a novel power side-channel DAC (PS-DAC) which is constructed from user-controllable short circuits in FPGAs and which manipulate overall system power through dynamic power dissipation. Alternately, similar PS-DACs are created using shift-register primitives(SRL16E) which manipulate system power through switching logic, for means of comparison with short-circuit-based PS-DACs. PS-DACs are created of various sizes using both short-circuit-based and shift-register-based methods. These PS-DACs are characterized in terms of output linearity,monotonicity, and frequency distortion. Applications explored in this thesis which use PS-DAC technology include a Simple Power Analysis (SPA) side-channel transmitter, and a frequency watermarking application. These applications serve as proof-of-concept for PS-DAC use in sidechannel communication applications.

The field programmable gate array (FPGA) is appealing as a computational platform because of its ability to be repurposed for a number of different applications and its relatively low design cost. Traditionally, FPGA vendors provide a set of electronic design automation (EDA) tools to assist customers with the implementation of their designs. These tools are necessarily general purpose, and the resulting tool flow does not provide the user much in the way of customization. Frameworks such as RapidSmith and Torc allow for the creation of custom CAD tools that are able to target actual Xilinx FPGA devices. However, they are built on the Xilinx Design Language (XDL), which was discontinued with the introduction of Xilinx's new tool suite Vivado. Instead, Vivado provides direct access to its data structures through a Tcl interface, as well as EDIF and Xilinx Design Constraint (XDC) files. This thesis discusses Vivado's ability to support a custom CAD tool framework similar to RapidSmith and Torc. It provides a detailed description of the CAD-related aspects of Vivado's Tcl API and shows how its command set can be used to integrate a custom CAD tool framework. This is demonstrated through the introduction of Tincr, a suite of two Tcl-based libraries that each encapsulate a separate method for implementing such a framework. The first is the TincrCAD library, a high-level CAD tool framework built within Vivado's Tcl environment. The second is TincrIO, a set of Tcl commands that comprise a file-based interface into Vivado, similar to XDL. These libraries are offered up as evidence that the Vivado Design Suite can provide a foundation for the implementation of custom CAD tools that operate on Xilinx FPGAs for the foreseeable future.

The open-source community is a valuable resource for many hobbyists and researchers interested in collaborating and contributing towards publicly available tools. In the area of field programmable gate arrays (FPGAs) this is no exception. Contributors seek to reverse-engineer the functions of large proprietary FPGA devices. An interesting challenge for open-source FPGA engineers has been reverse-engineering the operation and bitstreams of digital signal processing (DSP) blocks located in FPGAs. SymbiFlow is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. For SymbiFlow, mapping logical multipliers to DSP blocks and generating DSP block bitstreams has been left unimplemented for the Artix-7 family of FPGAs. This research seeks to rectify this shortcoming by introducing DSP information for the place and route functions into SymbiFlow. By delving into the SymbiFlow architecture definitions and creating functioning FPGA assembly code (FASM) files for Project X-Ray, a bitstream generator for Artix-7, we have been able to determine the desired output of the open-source Versatile Place & Route tool that will generate a working DSP bitstream. We diagnose and implement changes needed throughout the SymbiFlow toolchain, allowing for DSP design bitstreams to be successfully generated with open-source tools.

No description available.

Embedded system designers require deterministic, real-time operating system (RTOS) support for the commonly available processing hardware. The Xilinx Zynq Extensible Processing Platform (EPP) offers software, hardware, and input/output (I/O) programmability on a single chip. The Xilinx Zynq EPP features a Dual ARM Cortex-A9 MPCore, Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) interconnect, and Xilinx Kintex-7 series Programmable Logic (PL) which provide the requisite capabilities for the increasing demands of embedded processing applications. The AMBA AXI4 interconnect provides high speed point to point interconnections between the ARM processor cores and the Field Programmable Gate Array (FPGA) structure allowing for rapid data transmission to optimize system performance. The incorporation of an RTOS ensures predictable execution times of applications. Benchmarks, such as the Rhealstone, were developed to provide designers with a method of evaluating and comparing these multitasking RTOSs running on various hardware platforms. This thesis research performs Rhealstone benchmarking and evaluates the AMBA AXI4 interconnect performance while executing FreeRTOS on the ARM core of the Zynq EPP device. / Electrical and Computer Engineering

Master of Science / We are in an ever-increasing demand for computing power to sustain our technological advancements. A significant driving factor of our progress is the size and speed of memory we possess. Modern computer architectures use DDR4-based DRAM (Dynamic Random Access Memory) to hold all the immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. Since the capacitors are prone to charge leakage, each bit must be frequently rewritten with its old value. A dedicated memory controller handles the periodic refreshes. If the cells aren't refreshed, the bits lose their charge and lose the information stored by flipping to either 0 or 1 (depending upon the design). Due to manufacturing variations, every tiny capacitor fabricated will have different physical characteristics. Charge leakage depends upon capacitance and other such physical properties. Hence, no two DRAM modules can have the same properties and decay pattern and cannot be reproduced again accurately. This DRAM attribute can be considered a source of 'Physically Unclonable Functions' and is sought after in the Cryptography domain. This thesis aims to characterize the decay patterns of commercial DDR4 DRAM modules. I implemented a custom System On Chip on AMD/Xilinx's ZCU104 FPGA platform to interface different DDR4 modules with a primitive memory controller (without refreshes). Additionally, I introduced electric and magnetic fields close to the DRAM module to investigate their effects on the decay characteristics.

Traditional hardware radios provide very rigid solutions to radio problems. Intelligent software defined radios, also known as cognitive radios, provide flexibility and agility compared to hardware radio systems. Cognitive radios are well suited for radio applications in a changing radio frequency environment, such as dynamic spectrum access. In this thesis, a cognitive radio is demonstrated where the system self reconfigures to demodulate a detected waveform. The GNU Radio framework is used to provide basic software defined radio building blocks and is supplemented with FPGA accelerators. The use of GNU Radio compliant hardware interfaces allows for seamless hardware/software radio deployments. Dynamic resource mapping allows radio designers to operate at a layer of abstraction above the physical radio implementation. By establishing lower level abstraction layers, future researchers can focus on larger picture concepts such as learning algorithms and behavioral models for the cognitive engine. / Master of Science