Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Οι συστοιχίες προγραμματιζόμενων πυλών (FPGAs) αποτελούν μια σημαντική τεχνολογία, η οποία επιτρέπει στους σχεδιαστές κυκλωμάτων την παραγωγή συγκεκριμένου σκοπού ολοκληρωμένων κυκλωμάτων σε σύντομο χρόνο. Tα σημαντικότερα των χαρακτηριστικών τους είναι η αρχιτεκτονική τους και η δυνατότητα σχεδιασμού τους μέσω υπολογιστών, η χαμηλή κατανάλωση ισχύος καθώς και το μικρό χρονικό διάστημα που απαιτείται για τον επαναπρογραμματισμό τους. Τα FPGAs είναι κατάλληλα σχεδιασμένα για ψηφιακές εφαρμογές φιλτραρίσματος. Η πυκνότητα των προγραμματιζόμενων αυτών συστημάτων είναι τέτοια ώστε πολύ μεγάλος αριθμός αριθμητικών πράξεων όπως αυτές που προκύπτουν μέσω ψηφιακού φιλτραρίσματος να μπορεί να εφαρμοστεί σε μία μόνο συσκευή. Τα πλεονεκτήματα των FPGA στην υλοποίηση ψηφιακών φίλτρων είναι μεταξύ άλλων οι υψηλότεροι ρυθμοί δειγματοληψίας από παραδοσιακούς DSP chip, το χαμηλότερο κόστος από μια μέτρια ASIC (Application Specific Integrated Circuit, Kύκλωμα οριζόμενο από εφαρμογή) για εφαρμογές μεγάλου όγκου, καθώς και η μεγαλύτερη ευελιξία από όλες τις εναλλακτικές προσεγγίσεις για την υλοποίηση των FIR φίλτρων. Σπουδαιότερο όλων είναι ότι προγραμματίζονται μέσα στο σύστημα και έχουν δυνατότητα επαναπρογραμματισμού για την υλοποίηση διαφόρων εναλλακτικών λειτουργιών φιλτραρίσματος. Στόχος της παρούσας διπλωματικής είναι να συνδυασθούν τεχνικές VLSI και ψηφιακής επεξεργασίας σήματος και μέσω κατανόησης της αρχιτεκτονικής του υπολογιστή να δημιουργηθεί μια χρήσιμη εφαρμογή. Επιλέχθηκε για τον λόγο αυτό: α) η ανάπτυξη ενός FIR φίλτρου σε γλώσσα περιγραφής υλικού, β) υλοποίησή του σε FPGA, γ) εισαγωγή αυτού σε ενσωματωμένο σύστημα και σύνδεση σε διάδρομο δεδομένων επεξεργαστή και δ) έλεγχος του φίλτρου με τη βοήθεια του επεξεργαστή μέσω γλώσσας υψηλού επιπέδου. Η συγγραφή του κώδικα του φίλτρου έγινε σε γλώσσα VHDL, με structural μεθόδους και η προσομοίωση του συστήματος στο Modelsim. Επιπροσθέτως χρησιμοποιήθηκε ο Project Navigator ISE της Xilinx για τον έλεγχο του κώδικα αλλά και τον προγραμματισμό του FPGA Spartan 3E Starter Board. Χρησιμοποιήθηκαν ακόμα τα υποπρογράμματα Plan Ahead και ChipScope Pro του ISE ώστε να ελεγχθεί η λειτουργία του κυκλώματος στο FPGA. To κύκλωμα τελικά εισάγεται σε ενσωματωμένο σύστημα με τη βοήθεια του εργαλείου σχεδίασης EDK της Xilinx και ελέγχεται η λειτουργία του προγραμματίζοντας τον επεξεργαστή Microblaze. Ακόμα ελέγχεται η λειτουργία του φίλτρου για διαφορετικούς συντελεστές FIR φίλτρων που χρησιμοποιούν διαφορετικά παράθυρα και συγκρίνονται οι «ιδανικές» τιμές που παράγονται από το Matlab με αυτές που παράγονται από το φίλτρο. Τέλος μετράται η ενέργεια (δυναμική και στατική) που καταναλώνεται κατά τη λειτουργία του κυκλώματος στο FPGA με τη βοήθεια του XPower Analyzer. / Field-programmable gate arrays (FPGAs) is a technology of great importance that allows the designers to produce specific purpose integrated circuits in a limited amount of time. The most important of their characteristics are their architecture and the ability of their design with the help of computers, the low power dissipation, as well as the need of a short amount of time to be reprogrammed. FPGAs are properly designed for digital filtering applications. The density of these programmable systems is such that a great amount of numerical calculations such as those that result via digital filtering can be applied to one device only. The advantages of FPGAs as for the implementation of digital filters is between others the great rates of sampling compared to traditional DSP chips, their low cost compared to a moderate ASIC (Application Specific Integrated Circuit) for applications that take up a large area, as well as the flexibility compared to alternative approaches for the implementation of FIR filters. Their most important characteristic is that they can be programmed on-chip and that they have the ability of being reprogrammed for the implementation of different filtering purposes. The aim of this thesis is to combine VLSI techniques and digital signal processing techniques and via the understanding of the computer architecture to create a useful application. To fulfill that purpose: a) a FIR filter was designed with the use of a hardware description language b) the filter was implemented by using an FPGA c) the filter was imported to an embedded system and it was connected to the bus of a microprocessor d) the filter was controlled by the microprocessor via a high-level programming language. The filter was designed using the VHDL language, specifically using structural methods, and its simulation was performed with Modelsim. Also the Project Navigator ISE of Xilinx was used to correct unwanted warnings and to program the FPGA Spartan 3E Starter Board. Some other subprograms of ISE were also used, such as Plan Ahead and ChipScope Pro in order to check the performance of the filter. The circuit is finally imported to an embedded system using the Embedded Developer’s Kit (EDK) of Xilinx. Microblaze was the microprocessor that was used to control the filter’s performance. Additionally, the performance of the filter is checked by using different coefficients of FIR filters by different windowing methods. The ideal values that are produced from Matlab are compared to those of the filter. Finally the power dissipation (static and dynamic) of the filter is measured using XPower Analyzer.

The growing number of players in Massively Multiplayer Online games puts a heavy load on the network infrastructure and the general-purpose CPU of the game servers. A game server’s network stack processing needs equal treatment to the game-related processing ability. It is a fact that the networkcommunication tasks on the CPU reach the same order of magnitude as the game-related tasks, and the computing capability of the CPU can be a factor that limits the maximum number of players. Therefore, CPU offloading is becoming vital. FPGAs play an essential role in dedicated computation and network communication due to their superiority in flexibility and computation-oriented efficiency. Thus, an FPGA can be a good hardware platform to implement a network stack to replace the CPU in processing the network computations. However, most commercial and open-source network stack IPs support only one or few connections. This thesis project explores a network server on FPGA, implemented in RTL, that can handle multiple connections, specialized in the TCP protocol. The design in this project adds a cached memory hierarchy that provides a filter against port numbers of multiple connections from the same application and an Application Layer Controller, based on an open-source Ethernet, to increase the number of TCP connections further. A proof of concept was built, and its performance was tested. As a result, the TCP server on the FPGA was designed to handle a maximum of 40 configurable connections, but only 25 connections could be maintained during operation due to operational latency constraints. This FPGA server solution provides a latency of 1 ms in LAN. The babbling idiot and out-of-order packet transfer tests from clientswere also performed to guarantee robustness. During testing, poor performance in Packet Loss and Packet Error Handling was noted. In the future, this issue needs to be addressed. In addition, further investigations of methods for expanding the cache need to be done to allow handling more clients. / Det växande antalet spelare i Massively Multiplayer Online-spel belastar nätverksinfrastrukturen och spelservrarnas CPU:er. En spelservers förmåga att bearbeta nätverksstacken måste behandlas lika med den spelrelaterade bearbetningsförmågan. Det är ett faktum att nätverkskommunikationsuppgifterna på processorn når samma storleksordning som de spelrelaterade uppgifterna, och processorns beräkningsförmåga kan vara en faktor som begränsar det maximala antalet spelare. Därför blir avlastning av CPU-viktig. FPGA:er spelar en viktig roll i dedikerad beräkning och nätverkskommunikation på grund av dess överlägsenhet vad gäller flexibilitet och beräkningsorienterad effektivitet. Således kan en FPGA vara en bra hårdvaruplattform för att implementera en nätverksstack, för att ersätta CPU:n vid bearbetning av nätverksberäkningsarna. Men, de flesta kommersiella och öppna källkodsnätverksstack- IP:er stöder dock bara en eller ett fåtal anslutningar. Detta examensarbete utforskar en nätverksserver på FPGA, implementerad mha RTL, som kan hantera flera anslutningar, specialiserad på TCP-protokollet. Designen i detta projekt lägger till en cachad minneshierarki som ger ett filter mot portnummer för flera anslutningar från samma applikation och en Application Layer Controller, baserad på öppen källkod för Ethernet, för att öka antalet TCP-anslutningar ytterligare. Ett proof of concept byggdes och dess prestanda testades. Som ett resultat designades TCP-servern på FPGA:n att kunna hantera maximalt 40 konfigurerbara anslutningar, men endast 25 anslutningar kunde bibehållas under drift på grund av driftsfördröjningar. Denna FPGA-serverlösning ger en latens på 1 ms i LAN. Tester inkluderande den babblande idioten och out-of-order paketöverföring från klienter utfördes också för att garantera robusthet. Under testningen noterades dålig prestanda i paketförlust och paketfelshantering. I framtiden måste denna fråga åtgärdas. Dessutom behöver ytterligare undersökningar av metoder för att utöka cachen göras för att kunna hantera fler klienter.

This work is part of an on-going research project at Virginia Commonwealth University in the field of Unmanned Aerial Vehicles (UAVs). The purpose of this thesis project is to port the previous generation of UAV autopilot from the Atmel FPSLIC platform to the Xilinx MicroBlaze platform in order to provide a test-bed that will accommodate future research projects. The tasks include porting the software from the AVR processor located on the FPSLIC to the MicroBlaze processor and implementing the hardware peripherals in Xilinx FPGA.The UAV equipped with the new autopilot can autonomously navigate through pre-defined waypoints and transmit the collected data back to the ground base station for analysis.

Modern embedded systems development poses new challenges to a designer due to the global reachability of the contemporary market. One product shipped to different countries or customers should satisfy varying conditions, standards and constraints. Variability of a developed system should be taken into account by a designer. In a case of the embedded heterogeneous systems, this problem becomes challenging. Along with the variability heterogeneity of a system introduces new tasks, which should be addressed during design process. In this work, we propose a technology independent design flow. The proposed solution is supported by state-of-the-art tools and takes into account variability, partitioning, interfacing and dependency resolving processes. This thesis is conducted as a case study. We explored a design process of an industrial project, identified existing challenges and drawbacks in the existing solutions. We propose a new approach to a design flow of heterogeneous embedded systems. Also, a tool, supporting the presented solution, is implemented, which would allow a developer to include this approach into everyday design flow in order to increase a development speed and enable a task automation.

<p>The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with <em>Rocket^TMIO</em> GPT transceivers tightly integrated with the FPGA logic. Since the actual DUT (Device Under Test) was not in place during the work, the transceivers of the FPGA were used for both sending and receiving data. The transmission was shown to be successful for both eight and ten bit data widths. At this stage a small skew between the data in the four channels was observed. This was solved by storing the information in separate memories, one for each of the channels, to make possible to later form the 4 bit words in the PC (MatLab). The memories were two port FIFOs writing in data at 240 MHz (10 bit data width) or 300 MHz (8 bit data width) and read out at 50 MHz.</p> / <p>Syftet med examensarbetet var att konfigurera en FPGA med höghastighetsportar så att data från en prototyp av en 4 bitars ΣΔ analog-till-digital omvandlare kan samlas in med en hastighet av 2.4 Gbps i var och en av fyra kanaler och att utveckla ett protokoll för överföring av dessa data från FPGAn till en PC för analys. Insamlade data ska sorteras i 4 bitars ord med en bit successivt tagen från var och en av kanalerna. Ett krav på dataöverföringen var att data i de fyra kanalerna skulle anlända synkront till FPGAn. En Virtex-5 FPGA på en LT110X plattfrom användes med <em></em>GTP transceivrar tätt integrerade med FPGA logiken. Då utrustningen som skulle testas inte var tillgänglig under tiden arbetet utfördes användes FPGAns transceivrar till att både sända och ta emot data. Överföring av data med både 8 och 10 bitars datavidd uppnåddes framgångsrikt. Data i de fyra kanalerna visade sig dock inte anlända synkront till mottagaren. Detta problem löstes genom att lagra informationen i separata minnen, ett för varje kanal, överföra data från minnena till PCn och där med hjälp av MatLab sortera dem till 4 bitars ord. Som minnen användes tvåportars FIFOn där data skrivs in med en hastighet av 240 MHz (10 bitars datavidd) eller 300 MHZ (8 bitars datavidd) och läses ut med en hastighet av 50 MHz.</p>

<p>The development in electronics increases the demand for good design methods and design tools in the field of electrical engeneering. To improve their design methods Ericsson Microwave Systems AB is interested in using computer tools to create a link between the specification and the implementation of a digital system in a FPGA. </p><p>Xilinx System Generator for DSP is a tool for implementing a model of a digital signalprocessing algorithm in a Xilinx FPGA. To evaluate Xilinx System Generator two testcases has been designed. </p><p>The testcases are selected to represent the FPGA designs made at Ericsson Microwave Systems. The testcases show that Xilinx System Generator can be used to effectivly implement a model made in Simulink in a FPGA from Xilinx. The result of the implementation is comparable to the implementation of VHDL code written by hand. </p><p>The use of tools for implementation of a model in hardware cause change in the design methods used at Ericsson Microwave Systems. The higher level of abstraction introduced by System Generator results in the design decisions made at system level having a higher impact on the final realization.</p>

<p>Today, wireless communications is used more then ever before. Wired systems are replaced with wireless versions. New methods and transmission standards are developed and tested. The purpose of this thesis is development of a flexible high-performance System Test Platformfor test of the SoCTRix Wireless LAN Transceiver. </p><p>The result is a Xilinx Virtex-II FPGA based System Test Platform board with CardBus PC Card interface to a computer. The hardware achieved has the following features:</p><p>- 8-layer PCB</p><p>- PCMCIA CardBus PC Card interface, enabling 133 MB/s data throughput</p><p>- 1M Gate Virtex-II FPGA with reprogrammable configuration memory</p><p>- Debugging via LEDs and Logic Analyzer connectors</p><p>- 2x SPI EEPROM</p><p>- 40 MHz system clock</p><p>- Easy connection of two daughter-boards</p><p>Specially designed for wireless transmitter development, can also be used for other computer related highperformance applications.</p>

<p>Digital Radio Frequency Memory (DRFM) is a technique widely used by the defense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sampling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design.</p><p>Hence, the purpose of this master's thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description language called VHDL. The method for this master's thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.</p>