The importance of securing hardware, particularly in the context of the Internet of Things (IoT), cannot be overstated in light of the increasing prevalence of low-level attacks. As the IoT industry continues to expand, security has become a more holistic concern, as evidenced by the wide range of attacks that we observed, from large-scale distributed denial-of-service attacks to data theft through monitoring a device's low-level behavior, such as power consumption. Traditional software-based security measures fall short in defending against the full spectrum of attacks, particularly those involving physical tampering with system hardware. This underscores the critical importance of proactively integrating attack vectors that encompass both hardware and software domains, with a particular emphasis on considering both the analog and digital characteristics of hardware. This thesis investigates system security from a hardware perspective, specifically examining how low-level circuit behavior and architectural design choices impact SRAM's data remanence and its implications for security. This dissertation not only identifies new vulnerabilities due to SRAM data remanence but also paves the way for novel security solutions in the ongoing "security arms race". I present an attack, volt boot, that executes cold-boot style short-term data remanence in on-chip SRAM without using temperature effect. This attack exploits the fact that SRAM's power bus is externally accessible and allows data retention using a simple voltage probe. Next, I present a steganography method that hides information in the SRAM exploiting long-term data remanence. This approach leverages aging-induced degradation to imprint data in SRAM's analog domain, ultimately resulting in hidden and plausibly deniable information storage in the hardware. Finally, I show how an adversary weaponizes SRAM data remanence to develop an attack on a hardware-backed security isolation mechanism. The following provides a brief overview of the three major contributions of this thesis: 1. Volt boot is an attack that demonstrates the vulnerability of on-chip SRAM due to the physical separation common in modern SoCs' power distribution networks. By probing external power pins (to the cache) of an SoC while simultaneously shutting down the main system power, Volt boot creates data retention across power cycles. On-chip SRAM can be a safe memory when the threat model considers traditional off-chip cold-boot-style attacks. This research demonstrates an alternative method for preserving information in on-chip SRAM through power cycles, expanding our understanding of data retention capabilities. Volt boot leverages asymmetrical power states (e.g., on vs. off) to force SRAM state retention across power cycles, eliminating the need for traditional cold boot attack enablers, such as low-temperature or intrinsic data retention time. 2. Invisible Bits is a hardware steganography technique that hides secret messages in the analog domain of SRAM embedded within a computing device. Exploiting accelerated transistor aging, Invisible Bits stores hidden data along with system data in an on-chip cache and provides a plausible deniability guarantee from statistical analysis. Aging changes the transistor's behavior which I exploit to store data permanently (ie long-term data remanence) in an SRAM. Invisible Bits presents unique opportunities for safeguarding electronic devices when subjected to inspections by authorities. 3. UntrustZone utilizes long-term data remanence to exfiltrate secrets from on-chip SRAM. An attacker application must be able to read retained states in the SRAM upon power cycles, but this needs changing the security privilege. Hardware security schemes, such as ARM TrustZone, erase a memory block before changing its security attributes and releasing it to other applications, making short-term data remanence attacks ineffective. That is, attacks such as Volt boot fail when hardware-backed isolation such as TEE is enforced. UntrustZone unveils a new threat to all forms of on-chip SRAM even when backed by hardware isolation: long-term data remanence. I show how an attacker systematically accelerates data imprinting on SRAM's analog domain to effectively burn in on-chip secrets and bypass TrustZone isolation. / Doctor of Philosophy / In computing systems, hardware serves as the fundamental bulwark against security breaches. The evolution in software security has compelled adversaries to seek potential vulnerabilities in the hardware.The infamous cold boot attack exemplifies such vulnerabilities, showcasing how adversaries exploit hardware to access runtime secrets, even when cryptographic algorithms protect the system's disk. In this attack, volatile main memory (DRAM) is `frozen' at extremely cold temperatures, allowing it to retain information even when disconnected from the victim machine. Subsequently, an adversary transfers this `frozen memory' to another machine to extract the victim's secrets. This classic case is among numerous sophisticated hardware vulnerabilities identified in recent years, highlighting the evolving challenge of securing hardware against ingenious attacks. This rise in hardware-based attacks across industry and academia underscores the importance of adopting a comprehensive approach to safeguard computing systems. This approach must encompass secure processor design, ensuring a trusted distribution chain, rigorous software security vetting, and protection against runtime side-channel leakage. Consequently, there is a growing emphasis in both industry and academia on prioritizing security in design decisions. My dissertation delves into the low-level hardware behaviors, particularly focusing on the data remanence phenomena of Static Random Access Memory (SRAM). By discovering new security vulnerabilities and proposing effective mitigation strategies, this thesis contributes to the ongoing effort to fortify computing systems against evolving threats that are rooted in the hardware. SRAM stands as a ubiquitous form of volatile memory found in most processors and microcontrollers, serving as a crucial component for temporary storage of instructions and data to facilitate rapid access. By design, SRAM forgets its contents upon a processor's power cycle and defaults to a state determined by low-level circuit behavior. However, this dissertation unveils the possibility of retaining on-chip information even after power cycling, leveraging inherent low-level circuit behaviors to create data retention. This revelation exposes major security implications, resulting in the following three key contributions: Firstly, I introduce the volt boot attack, which exploits the vulnerability of on-chip SRAM, particularly to physical separation in modern System on Chip (SoC) power distribution networks. We conventionally assume that on-chip SRAM is secure against off-chip cold-boot attacks, but volt boot demonstrates the feasibility of achieving a similar state without traditional prerequisites such as low temperatures or long intrinsic data retention times. Subsequently, I propose a data hiding technique---invisible Bits, which leverages accelerated device wear out to embed data into the transistors of SRAM. This method introduces a novel form of hardware-based steganography, concealing data within the analog domain alongside digital system data. Lastly, I show how accelerated device aging can be weaponized to design a sophisticated attack aimed at extracting secrets from a Trusted Execution Environment (TEE) like ARM TrustZone. While short-term data remanence attacks such as Volt boot are rendered ineffective against hardware-backed isolation enforced by TEEs, UntrustZone harnesses the methodologies and tools from preceding works to induce long-term data remanence. This poses a new threat to on-chip cryptography that stores secrets on chip, even when fortified by hardware isolation mechanisms, such as ARM TrustZone.

Considerable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption. Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion. / Master of Science

L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire dans la diminution de la fiabilité des composants électroniques aussi bien dans l’environnement radiatif spatial que terrestre. Cette étude porte sur la modélisation des mécanismes physiques qui conduisent à ces aléas logiques (en anglais "Soft Errors"). Ces modèles sont utilisés dans une plateforme de simulation,appelée TIARA (Tool suIte for rAdiation Reliability Assessment), qui a été développée dans le cadre de cette thèse. Cet outil est capable de prédire la sensibilité de nombreuses architectures de circuits (SRAM,Flip-Flop, etc.) dans différents environnements radiatifs et sous différentes conditions de test (alimentation, altitude, etc.) Cette plateforme a été amplement validée grâce à la comparaison avec des mesures expérimentales effectuées sur différents circuits de test fabriqués par STMicroelectronics. La plateforme TIARA a ensuite été utilisée pour la conception de circuits durcis aux radiations et a permis de participer à la compréhension des mécanismes des aléas logiques jusqu’au noeud technologique 20nm. / Aggressive integrated circuit density increase and power supply scaling have propelled Single Event Effects to the forefront of reliability concerns in ground-based and space-bound electronic systems. This study focuses on modeling of Single Event physical phenomena. To enable performing reliability assessment, a complete simulation platform named Tool suIte for rAdiation Reliability Assessment (TIARA) has been developed that allows performing sensitivity prediction of different digital circuits (SRAM, Flip-Flops, etc.) in different radiation environments and at different operating conditions (power supply voltage,altitude, etc.) TIARA has been extensively validated with experimental data for space and terrestrial radiation environments using different test vehicles manufactured by STMicroelectronics. Finally, the platform has been used during rad-hard digital circuits design and to provide insights into radiation-induced upset mechanisms down to CMOS 20nm technological node.

Efeitos causados pela interação da radiação ionizante em dispositivos eletrônicos consis- tem numa preocupação crescente em diversos segmentos, como as aplicações aeroespaci- ais e em física de altas energias. Entre os efeitos de radiação induzidos por íons pesados estão os chamados de Efeitos de Eventos Isolados (Single Event Effects - SEE), em que o impacto de um único íon pode ser capaz de gerar um efeito observável, através da elevada deposição de energia e consequente geração de pares elétron-lacuna. O estudo destes efeitos requer um acelerador de partículas capaz de prover feixes uniformes de íons pesados com baixo fluxo. Neste trabalho, desenvolvemos um sistema para produ- ção de feixes de íons pesados para estudar SEE no Acelerador Pelletron 8UD, utilizando as técnicas de desfocalização e espalhamento múltiplo em folhas de ouro. O sistema foi projetado para prover feixes com intensidades entre 10 2 e 10 5 partículas/s/cm 2 com uniformidade maior que 90% numa área circular de diâmetro de 1,5 cm, operando em regime de alto-vácuo. Um manipulador de amostras permite a movimentação do dispo- sitivo sob teste com precisão de 2,5 m e um sistema de aquisição de dados dedicado foi desenvolvido, permitindo a automação de medidas. O sistema foi caracterizado com feixes de 1 H, 12 C, 16 O, 19 F, 28 Si, 35 Cl e 63 Cu a várias energias, apresentando fluxo e uni- formidade adequados aos experimentos em diversas configurações de focalização e folhas espalhadoras, e tem sido utilizado por diversos grupos de pesquisa. O novo sistema foi utilizado para estudar o efeito das camadas de isolamento e metalização na coleta de carga e geração de eventos observáveis em um dispositivo analógico e em um disposi- tivo digital, de modo a estabelecer metodologias de trabalho adequadas para estudos precisos de mecanismos de ocorrência de efeitos de radiação. O dispositivo analógico estudado foi um transistor p-MOS, onde o sinal de corrente induzido pelo impacto de íons diversos foi analisado de modo a obter a seção de choque de eventos e a cargaix gerada, permitindo determinar a espessura da camada de metalização em 1,28(2) m, e a camada de coleta de carga dependente do LET e alcance da partícula incidente, variando entre 6,0 e 11,0 m. O dispositivo digital estudado foi uma memória SRAM 28nm, onde foi observada uma forte dependência da seção de choque de eventos com a penetração do feixe no dispositivo. Associando as camadas de metalização e isolamento a um meio efetivo de interação, obteve-se que toda a área sensível do dispositivo só pode ser excitada, isto é, nela ocorrerem eventos observáveis, para partículas com alcance, no meio efetivo, entre 14 e 20 m, embora partículas com alcance de até 10 m sejam capazes de sensibilizar até 50% da área ativa do dispositivo. / Effects on electronic devices caused by interactions of ionizing radiation are a main concern in several fields, such as aerospace applications and high-energy physics. Among the heavy-ion induced radiation effects are the Single Event Effects, in which a strike of a single ion can be enough to generate an observable effect, as a result of the high energy deposition and thus electron-hole pairs generation. The study of these effects requires the use of uniform, low-flux particle beams. In this work, we developed a system for production of heavy ion beams for SEE studies at Pelletron 8UD accelerator, through the defocusing and multiple scattering in gold foil techniques. The setup can provide ion beams with intensities ranging from 10 2 e 10 5 particles/s/cm 2 with uniformity better than 90% in an circular area of 1.5 cm diameter, operating under high-vacuum. A sample manipulador allows device under test positioning with a precision of 2.5 m, and a dedicated data acquisition system was developed, allowing measurement automation. The system was characterized with 1 H, 12 C, 16 O, 19 F, 28 Si, 35 Cl and 63 Cu ion beams at several energies, presenting flux and uniformity adequate for SEE studies in many different configurations, and it is being used by several research groups. The new facility was used to study the effect of isolation and metalization layers in charge collection and observable events generation in an analog and in a digital device, in order to establish proper metodologies for precise studies of radiation effects mecanisms. The analog device studied was a p-MOS transitor, from which the heavy-ion impact induced current signal was analised to obtain cross-section and colected charge, allowing to determine metalization layer thickness to be 1.28(2) m, and charge collection dependency on particle LET and range, varying from 6.0 to 11.0 m. The digital device studied was a 28nm SRAM memory, where a strong dependency of cross-section with particle range in the device was observed. Associating to the metal and insulating layers an effectivexi medium, it was observed that the complete sensitive area can be excited only by particle with ranges in effective medium between 14 and 20 m, although particles with ranges up to 10 m are capable of sensibilizing up to 50% of devices active area.

<p>Vid implementeringar av FIFO-arkitekturer har asynkrona FIFO-konstruktioner använts. Denna lösningsmetod har visat sig innehålla en del brister vid tillämpning på höghastighets system, vilket ledde till att synkrona FIFOn började ersätta asynkrona FIFOn. </p><p>Den synkrona arkitekturen har samma funktonalitet som de asynkrona typerna med fördelar som högre hastighet och enklare gränssnitt. </p><p>I rapporten har olika FIFO-konstruktioner behandlats och jämförelser har gjorts mellan synkrona och asynkrona arkitekturer. Det vid ISY konstruerade SRAM-minnet har sedan avgjort vilken typ av FIFO-arkitektur som varit bäst lämpad för implementering. </p><p>Det implementerade FIFO-minnet ordnar indata- och utdataflöden till ett enkelports SRAM-minne på 256 ord med 16 bitar per ord.</p> / <p>Previous implementations of FIFO-architectures has often been asynchronous FIFO-constructions. This method has some limitations in high speed systems. Instead synchronous FIFOs has more and more replaced asynchronous FIFOs. </p><p>The synchronous architecture has the same features as the asynchronous but with advantages such as higher speed and simplified interface. </p><p>In the report different types of FIFO-constructions has been studied and comparison between synchronous and asynchronous architectures has been done. The memory unit developed by ISY decided which FIFO-architecture that were best suited for the implementation. </p><p>The implemented FIFO-memory arrange in- and outdataflow to a single-port SRAM memory containing 256 words with 16 bits per word.</p>

Vid implementeringar av FIFO-arkitekturer har asynkrona FIFO-konstruktioner använts. Denna lösningsmetod har visat sig innehålla en del brister vid tillämpning på höghastighets system, vilket ledde till att synkrona FIFOn började ersätta asynkrona FIFOn. Den synkrona arkitekturen har samma funktonalitet som de asynkrona typerna med fördelar som högre hastighet och enklare gränssnitt. I rapporten har olika FIFO-konstruktioner behandlats och jämförelser har gjorts mellan synkrona och asynkrona arkitekturer. Det vid ISY konstruerade SRAM-minnet har sedan avgjort vilken typ av FIFO-arkitektur som varit bäst lämpad för implementering. Det implementerade FIFO-minnet ordnar indata- och utdataflöden till ett enkelports SRAM-minne på 256 ord med 16 bitar per ord. / Previous implementations of FIFO-architectures has often been asynchronous FIFO-constructions. This method has some limitations in high speed systems. Instead synchronous FIFOs has more and more replaced asynchronous FIFOs. The synchronous architecture has the same features as the asynchronous but with advantages such as higher speed and simplified interface. In the report different types of FIFO-constructions has been studied and comparison between synchronous and asynchronous architectures has been done. The memory unit developed by ISY decided which FIFO-architecture that were best suited for the implementation. The implemented FIFO-memory arrange in- and outdataflow to a single-port SRAM memory containing 256 words with 16 bits per word.

Cette thèse s'intéresse en premier lieu à l'analyse des effetsfonctionnels des erreurs dans laconfiguration de FPGAs à base de SRAM. Ces erreurs peuvent provenir deperturbations naturelles(rayonnements, particules) ou d'attaques volontaires, par exemple avecun laser. La famille Virtex IIde Xilinx est utilisée comme premier cas pratique d'expérimentation,puis une comparaison est réaliséeavec la famille AT40K de chez ATMEL. Ceci a permis de mieux comprendrel'impact réel dedifférentes sources de perturbations, et les motifs d'erreur devantréellement être pris en compte pouraméliorer la robustesse d'un circuit implanté sur ce type detechnologie. Cette étude a nécessité ledéveloppement d'outils de conception spécifiques, permettantd'automatiser les analyses. Uneméthodologie innovante est proposée pour l'évaluation de lasensibilité de la mémoire de configurationaux SEUs : une classification des bits de configuration est établie enfonction des effets produits parleur inversion sur le fonctionnement normal de l'application. Cecipermet de déterminer les zones lesplus critiques, autorisant le développement de stratégies deprotection sélectives et à faible coût. / This thesis deals primarily with the analysis of the functionaleffects of errors in the configuration ofSRAM-based FPGAs. These errors can be due either to naturalperturbations (radiations, particles) orto malicious attacks, for example with a laser. The Xilinx Virtex IIfamily is used as first case study,then a comparison is made with the ATMEL AT40K family. This workallowed us a betterunderstanding of the real impact of perturbations, and of the errorpatterns that need to be taken intoaccount when improving the robustness of a circuit implemented on thistype of technology. Thisstudy required the development of specific design tools to automatethe analyses. An innovativemethodology is proposed for the evaluation of the configuration memorysensitivity to SEUs: aclassification of configuration bits is made with respect to theeffects produced on the application by asingle bit-flip. This enables us to identify the most critical areas,and to propose selective hardeningsolutions, improving the global reliability of the application at low cost.

La course à la miniaturisation requiert l'introduction d'architectures de transistors innovantes enremplacement des technologies conventionnelles sur substrat de silicium. Ainsi la technologie UTBB-FDSOI permet d'améliorer notablement l'intégrité électrostatique et assure une transition progressive vers les structures 3D multigrilles. Ces dispositifs diffèrent des structures conventionnelles par la présence d'un oxyde enterré qui va non seulement modifier l'électrostatique mais également introduire une nouvelle interface de type Si/SiO2 sujette à d'éventuelles dégradations. Par ailleurs, la réduction des dimensions des transistors s'accompagne d'une augmentation de la dispersion des paramètres électriques. En parallèle, le vieillissement de ces transistors introduit une forme additionnelle de variabilité : la variabilité temporelle, qu'il convient d'intégrer à cette composante moyenne de dégradation. Ce travail de thèse est développé sur quatre chapitres, où nous nous intéressons dans le premier chapitre aux évolutions technologiques nécessaires pour passer des technologies CMOS standards (40LP, 28LP) à cette technologie UTBB-FDSOI. Puis dans le second chapitre, nous abordons la dégradation moyenne des transistors et l'impact de l'architecture sur la fiabilité des dispositifs, étudiés sur les mécanismes de dégradations NBTI et HCI. Le troisième chapitre donne au niveau transistor une description analytique et physique de la variabilité temporelle induite par le NBTI. Enfin, cette variabilité temporelle est intégrée au niveau cellules SRAM dans le quatrième chapitre afin de prédire les distributions des tensions minimums de fonctionnement (Vmin) des mémoires SRAM. / The classical CMOS structure is reaching its scaling limits at the 20nm node and innovative architectures of transistors are required to replace these conventional Bulk transistors. UTBB-FDSOI transistors can improve significantly the electrostatic integrity and ensure a smooth transition to 3D multi-gates devices that will be required for sub-10nm nodes. The main difference compared to conventional transistor is related to the integration of a buried oxide (BOX) underneath the silicon film. This latter impacts the electrostatic behavior of these devices and introduces an additional Si/SiO2 interface which may be degraded due to ageing. It is then necessary to evaluate its impact on the NBTI and HCI reliability mechanisms. Besides, transistor scaling leads to an increasing variability which translates into an increased dispersion of the electrical parameters of the transistors. Meanwhile, time dependent variability due to ageing needs to be added to the average degradation component. This PhD done in STMicroelectronics R&D center is divided into four chapters: in the first one, the main technological developments necessary to keep on sustaining Moore's law requirements resulting in the UTBBFDSOI structure introduction is discussed. Then in the second chapter the architecture impact on the average reliability mechanism is discussed at transistor and Ring Oscillators' levels. In the third chapter, the time dependent variability due to NBTI is described and compared to time-zero variability. Finally the last chapter focuses on the SRAM cells reliability and a method is developed to predict minimum operating voltage (Vmin) distributions of SRAM memory.

Aujourd'hui, les mémoires SRAM sont faites avec les technologies les plus rapides et sont parmi les éléments les plus importants dans les systèmes complexes. Les cellules SRAM sont souvent conçues en utilisant les dimensions minimales du nœud technologique. En conséquence, les SRAM sont plus sensibles à de nouveaux phénomènes physiques qui se produisent dans ces technologies, et sont donc extrêmement vulnérables aux défauts physiques. Afin de détecter si chaque composant est défectueux ou non, des procédures de test de haut coût sont employées. Différentes questions liées à cette procédure de test sont compilées dans ce document. Un des principaux apports de cette thèse est d'établir une méthode pour définir les conditions environnementales lors de la procédure de test afin de capter des défauts non-déterministe. Puisque des simulations statistiques sont souvent utilisées pour étudier des défauts non-déterministes, une méthode de simulation statistique efficace a été spécialement conçue pour la cellule SRAM. Dans cette thèse, nous traitons aussi la caractérisation de fautes, la caractérisation de la variabilité et la tolérance aux fautes. / Nowadays, Static Random Access Memories (SRAM) are made with the fastest technologies and are among the most important components in complex systems. SRAM bit-cell transistors are often designed using the minimal dimensions of the technology node. As a consequence, SRAMs are more sensitive to new physical phenomena that occur in these technologies, and hence are extremely vulnerable to physical defects. In order to detect whether each component is defective or not, high cost test procedures are employed. Different issues related to this test procedure were studied during this thesis, and are compiled in this document. One of the main contributions of this thesis was to establish a method to set the environmental conditions during the test procedure in order to capture non-deterministic faults. Since statistical simulations are often used to deal with non-deterministic faults, an efficient statistical simulation method was specially conceived for the 6 transistors SRAM bit-cell. In this thesis, we equally deal with fault characterization, variability characterization and fault tolerance.

De nos jours, les mémoires embarquées sont les composants les plus denses dans les "System-On-Chips" (SOCs), représentant actuellement plus que 90% de leur superficie totale. Parmi les différents types de mémoires, les SRAMs sont très largement utilisées dans la conception des SOCs, particulièrement en raison de leur haute performance et haute densité d'intégration. En revanche, les SRAMs conçues en utilisant des technologies submicroniques sont devenus les principaux contributeurs de la consommation d'énergie globale des SOCs. Par conséquent, un effort élevé est actuellement consacré à la conception des SRAMs à faible consommation. En plus, en raison de leur structure dense, les SRAMs sont devenus de plus en plus susceptibles aux défauts physiques comparativement aux autres blocs du circuit, notamment dans les technologies les plus récentes. Par conséquent, les SRAMs se posent actuellement comme le principal détracteur du rendement des SOCs, ce qui cause la nécessité de développer des solutions de test efficaces ciblant ces dispositifs.Dans cette thèse, des simulations électriques ont été réalisées pour prédire les comportements fautifs causés par des défauts réalistes affectant les blocs de circuits spécifiques aux technologies SRAM faible consommation. Selon les comportements fautifs identifiés, différents tests fonctionnels, ainsi que des solutions de tests matériels, ont été proposés pour détecter les défauts étudiés. Par ailleurs, ce travail démontre que les circuits d'écriture et lecture, couramment incorporés dans les SRAMs faible consommation, peuvent être réutilisés pour augmenter le stress dans les SRAMs lors du test, ce qui permet d'améliorer la détection des défauts affectant la mémoire. / Nowadays, embedded memories are the densest components within System-On-Chips (SOCs), accounting for more than 90% of the overall SOC area. Among different types of memories, SRAMs are still widely used for realizing complex SOCs, especially because they allow high access performance, high density and fast integration in CMOS designs. On the other hand, high density SRAMs designed with deep-submicrometer technologies have become the main contributor to the overall SOC power consumption. Hence, there is an increasing need to design low-power SRAMs, which embed mechanisms to reduce their power consumption. Moreover, due to their dense structure, SRAMs are more are more prone to defects compared to other circuit blocks, especially in recent technologies. Hence, SRAMs are arising as the main SOC yield detractor, which raises the need to develop efficient test solutions targeting such devices.In this thesis, failure analysis based on electrical simulations has been exploited to predict faulty behaviors caused by realistic defects affecting circuit blocks that are specific to low-power SRAMs, such as power gating mechanisms and voltage regulation systems. Based on identified faulty behaviors, efficient March tests and low area overhead design for testability schemes have been proposed to detect studied defects. Moreover, the reuse of read and write assist circuits, which are commonly embedded in low-power SRAMs, has been evaluated as an alternative to increase stress in the SRAM during test phase and then improve the defect coverage.