The non-isolated POL converters are widely used in computers, telecommunication systems, portable electronics, and many other applications. These converters are usually constructed using discrete components, and operated at a lower frequency around 200 ~ 600 kHz to achieve a decent efficiency at the middle of 80's%. The passive components, such as inductors and capacitors, are bulky, and they occupy a considerable foot-print. As the power demands increase for POL converters and the limited real estate of the mother board, the POL converters must be made significantly smaller than what they have demonstrated to date. To achieve these goals, two things have to happen simultaneously. The first is a significant increase in the switching frequency to reduce the size and weight of the inductors and capacitors. The second is to integrate passive components, especially magnetics, with active components to realize the needed power density. Today, this concept has been demonstrated at a level less than 5A and a power density around 300-700W/in3 by using silicon-based power semiconductors. This might address the need of small hand-held equipment such as PDAs and smart phones. However, it is far from meeting the needs for applications, such as netbook, notebook, desk-top and server applications where tens and hundreds of amperes are needed. After 30 years of silicon MOSFET development, the silicon has approached its theoretical limits. The recently emerged GaN transistors as a possible candidate to replace silicon devices in various power conversion applications. GaN devices are high electron mobility transistors (HEMT) and have higher band-gap, higher electron mobility, and higher electron velocity than silicon devices, and offer the potential benefits for high frequency power conversions. By implementing the GaN device, it is possible to build the POL converter that can achieve high frequency, high power density, and high efficiency at the same time. GaN technology is in its early stage; however, its significant gains are projected in the future. The first generation GaN devices can outperform the state-of-the-art silicon devices with superior FOM and packaging. The objective of this work is to explore the design of high frequency, high power density 12 V input POL modules with GaN devices and the 3D integration technique. This work discusses the fundamental differences between the enhancement mode and depletion mode GaN transistors, the effect of parasitics on the performance of the high frequency GaN POL, the 3D technique to integrate the active layer with LTCC magnetic substrate, and the thermal design of a high density module using advanced substrates with improved thermal conductivity. The hardware demonstrators are two 12 V to 1.2 V highly integrated 3D POL modules, the single phase 10 A module and two phase 20 A module, all built with depletion mode GaN transistors and low profile LTCC inductors. / Master of Science

Point-of-load (POL) converters have been used extensively in IT products. Today, almost every microprocessor is powered by a multi-phase POL converter with high output current, which is also known as voltage regulator (VR). In the state-of-the-art VRs, the circuits are mostly constructed with discrete components and situated on the motherboard, where it can occupy more than 1/3 of the footprint of the motherboard. A compact POL is desirable to save precious space on motherboards to be used for some other critical functionalities. Recently, industry has released many modularized POL converters, in which the bulky inductor is integrated with the active components to increase the power density. This concept has been demonstrated at current levels less than 5A and power density around 600-1000W/in³. This might address the needs of small hand-held equipment such as smart phones, but it is far from meeting the needs for the applications such as laptops, desktops and servers, where tens and hundreds of amperes are needed. A 3D integrated POL module with an output current of tens of ampere has been successfully demonstrated at the Center for Power Electronic Systems (CPES), Virginia Tech. In this structure, the inductor is elaborated with low temperature co-fire ceramic (LTCC) ferrite, as a substrate where the active components are placed. The lateral flux inductor is proposed to achieve both a low profile and high power density. Generally, the size of the inductor can be continuously shrunk by raising the switching frequency. The emerging gallium-nitride (GaN) power devices enable the creation and use of a multi-MHz, high efficiency POL converter. This dissertation firstly explores the LTCC inductor substrate design in the multi-MHz range for a high-current POL module with GaN devices. The impacts of different frequencies and different LTCC ferrite materials on the inductor are also discussed. Thanks to the DC flux cancellation effect, the inverse coupled inductor further improves the power density of a 20A, 5MHz two-phase POL module to more than 1kW/in³. An FEA simulation model is developed to study the core loss of the lateral flux coupled inductor, which shows the inverse coupling is also beneficial for core loss reduction. The ceramic-based 3D integrated POL module, however, is not widely adopted in industrial products because of the relatively high cost of the LTCC ferrite material and complicated manufacturing process. To solve that problem, a printed circuit board (PCB) inductor substrate with embedded alloy flake composite core is proposed. The layerwise magnetic core is laminated into a multi-layer PCB, and the winding of the inductor then is formed by the copper layers and conventional PCB vias. As a demonstration of system integration, a 20A, 1.5MHz integrated POL module is designed and fabricated based on a 4-layer PCB with embedded flake core, which realizes more than 85% efficiency and 600W/in³ power density. The application of standardized PCB processes reduces the cost for manufacturing the integrated modules due to the easy automation and the low temperature manufacturing process. Combining the PCB-embedded coupled inductor substrate and advanced control strategy, the two-phase 40A POL modules are elaborated as a complete integrated laptop VR solution. The coupled inductor structure is slightly modified to improve its transient performance. The nonlinearity of the inductance is controlled by adding either air slots or low permeability magnetic slots into the leakage flux path of the coupled inductor. Then the leakage flux, which determines the transient response of the coupled inductor, can be well controlled. If we directly replace the discrete VR solution with the proposed integrated modules, more than 50% of the footprint on the motherboard can be saved. Although the benefits of the lateral flux inductor have been validated in terms of its high power density and low profile, the planar core is excited under very non-uniform flux. Some parts of the core are even pushed into the saturation region, which totally goes against the conventional sense of magnetic design. The final part of this dissertation focuses on evaluating the performance of the planar core with variable flux. The counterbalance between DC flux and AC flux is revealed, with which the AC flux and the core loss density are automatically limited in the saturated core. The saturation is essentially no longer detrimental in this special structure. Compared with the conventional uniform flux design, the variable flux structure extends the operating point into the saturation region, which gives better utilization of the core. In addition, the planar core with variable flux also provides better thermal management and more core loss reduction under light load. As conclusions, this research first challenges the conventional magnetic design rules, which always assumes uniform flux. The unique characteristics and benefits of the variable flux core are proved. As an example of taking advantages of the lateral flux inductor, the PCB integrated POL modules are proposed and demonstrated as a high-density VR solution. The integrated modules are cost-effective and ready to be commercialized, which could enable the next technological innovation for the whole computing and telecom industry. / Ph. D.

The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die. One of the largest issues with prebond die testing is that, to save power, a single die may not have a complete clock distribution network until bonding. This thesis addresses the problem of prebond die testability by ensuring the clock distribution network on a single die will operate with low skew during testing and at a reduced power consumption during operation as compared to a full clock network. The development of a Delay Lock Loop is detailed and used to synchronize disconnected clock networks on a prebond die. This succeeds in providing a test clock network that operates with a skew that is sufficiently close to the target postbond skew. Additionally, a scheme to increase interdie bandwidth by multiplexing Through-Silicon Vias (TSVs) by the system clock is presented. This technique allows for great increase in the number of effective signal TSVs while imposing a negligible area overhead causing no performance degradation.

3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore’s law trajectory. 3D Integrated Circuits (ICs) can be realized using the Through Silicon Via (TSV) approach. In order to extract the full benefits of 3D and for better yield, it has been suggested that the TSVs should be arranged as bundles rather than parallel TSVs. TSVs are required to route the signals through different dies in a multi-tier 3D IC. TSVs are excellent but scarce electrical conductors. Hence, it is important to utilize these resources very efficiently. In high performance 3D ICs, signaling techniques play a crucial role in determining the overall performance of the system. In this work, 3x3 and 4x4 TSV bundles are considered. Electrical parasitics of TSV bundles are extracted using Ansoft Q3D Extractor. Various techniques for signaling over TSV bundles are analyzed in this work. Performance, energy and robustness are the crucial aspects to be considered for analyzing a signaling technique. For performance analysis, maximum data rate for each of the signaling techniques is obtained and the dominant factors that determine these values are identified. 3D integration is fairly a new field and does not have common standards. Different research groups (both academic and industry) across the globe have different manufacturing technologies to suit their needs. In this work, we obtain the electrical parasitics of TSV bundles for different TSV radii ranging from 1mm to 15mm. The TSV radius for most of the 3D integration technologies falls within this range. Maximum data rates are determined for different TSV radii ranging from 1mm to 15mm. This study across different TSV radii helps in choosing a better signaling technique for a particular TSV radius depending on the design goals. Energy/bit for each of the signaling techniques is obtained for a common data rate of 10Gbps Pseudo Random Bit Sequence (PRBS) input. For robustness analysis, the impact of process, voltage and temperature variations between driver and receiver circuits is analyzed. Ansoft Q3D extractor, NCSU 45nm PDK and HSPICE simulation tool are used. From the simulation results, it is observed that a differential technique is beneficial for smaller radii in terms of maximum data rate that can be obtained. For a radius above 7mm, single ended current mode signaling gives a better data rate. Low swing single ended signaling techniques consume less energy but suffer slightly more due to process variations compared to full swing voltage mode signaling. In terms of robustness to supply noise, differential signaling is more robust compared to single ended techniques. An increase in the temperature reduces the data rates of both single ended and differential signaling techniques. Hence, depending on the TSV radius of target technology and process and environment variations, an optimum signaling technique can be chosen.

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XLI

Current trends in electronic industry, such as Internet of Things (IoT) and Cloud Computing call for high interconnect bandwidth, increased number of active devices and high IO count. Hence the integration of on silicon optical waveguides becomes an alternative approach to cope with the performance demands. The application and fabrication of horizontal (planar) and vertical (Through Silicon Vias - TSVs) optical waveguides are discussed here. Coupling elements are used to connect both waveguide structures. Two micro-structuring technologies for integration of coupling elements are investigated: μ-mirror fabrication by nanoimprint (i) and dicing technique (ii). Nanoimprint technology creates highly precise horizontal waveguides with polymer (refractive index nC = 1.56 at 650 nm) as core. The waveguide ends in reflecting facets aligned to the optical TSVs. To achieve Total Internal Reflection (TIR), SiO2 (nCl = 1.46) is used as cladding. TSVs (diameter 20-40μm in 200-380μm interposer) are realized by BOSCH process1, oxidation and SU-8 filling techniques. To carry out the imprint, first a silicon structure is etched using a special plasma etching process. A polymer stamp is then created from the silicon template. Using this polymer stamp, SU-8 is imprinted aligned to vertical TSVs over Si surface.Waveguide dicing is presented as a second technology to create coupling elements on polymer waveguides. The reflecting mirror is created by 45° V-shaped dicing blade. The goal of this work is to develop coupling elements to aid 3D optical interconnect network on silicon interposer, to facilitate the realization of the emerging technologies for the upcoming years.

La fabrication des dispositifs en microélectronique implique aujourd’hui une architecture tridimensionnelle : « l’intégration 3D ». La mise en œuvre de cette technologie peut être limitée par des questions d’intégrité mécanique des dispositifs durant les processus de fabrication. En effet, déposer plusieurs couches aux propriétés thermomécaniques distinctes et à différentes températures ou amincir le substrat de silicium pour réaliser des interconnexions sont autant d’étapes à contrôler pour prévenir des décohésions le long d’interfaces, des distorsions des wafers ou encore des contraintes induites trop grandes et garantir la fiabilité des composants.Dans ce travail nous avons abordé ces questions en considérant des dépôts de nature diverse (métallique, oxyde ou polymère) pour lesquels une réponse thermoélastique est considérée, dépendant de la température le cas échéant. Un modèle semi-analytique « Sigmapps », exploitable en salle blanche, a été développé pour prédire la déformée induite au cours des procédés de dépôt et prédire les contraintes induites dans chaque couche, permettant également d’identifier les propriétés thermoélastique d’une couche dans le cadre d’une « approche inverse ». Dans ce cas, des mesures expérimentales sont nécessaires et ont été menées au LETI. Dans une deuxième partie, nous avons étudié le phénomène d’instabilité d’une structure multicouche, comportant des contraintes internes. Ici, le chargement thermique d’un bicouche a été considéré comme « cas d’étude » et nous nous sommes attachés à prédire la température pour laquelle une instabilité apparaissait jusqu’à la prédiction de l’état « post-critique ». Là aussi, l’approche est semi-analytique pour garantir son utilisation, simple, en environnement de salle blanche. Le problème de la criticité d’un dépôt sur la stabilité d’un wafer peut également être abordé. Il est ainsi possible d’orienter le choix des matériaux à intégrer et leurs épaisseurs pour garantir l’intégrité des dispositifs et optimiser les séquences de fabrication. / The fabrication of devices in microelectronics today involves a three-dimensional architecture: "3D integration". The implementation of this technology may be limited by issues of mechanical integrity of the devices during manufacturing processes. Indeed, the deposit of several layers with distinct thermomechanical properties and at different temperatures or thinning the silicon substrate to achieve interconnections are all steps to control in order to prevent decohesions along interfaces, distortions of wafers or too high induced stresses and to guarantee the reliability of the components.In this work we have approached these questions by considering deposits of various nature (metal, oxide or polymer) for which a thermoelastic response is considered, depending on the temperature if necessary. A semi-analytical model "Sigmapps", exploitable in a clean room, was developed to predict the deformation induced during the deposition processes and to predict the stresses induced in each layer, also enabling the identification of thermoelastic properties of a layer by "reverse approach". In this case, experimental measurements are necessary and were conducted at LETI. In a second part, we studied the phenomenon of instability of a multilayer structure, including internal stresses. Here, the thermal loading of a bilayer has been considered as a "case study" and we have predicted the temperature at which instability appeared until the prediction of the "post-critical" state. Here too, the approach is semi-analytical to ensure its simple use in a clean room environment. The problem of the criticality of a deposit on the stability of a wafer can also be addressed. It is thus possible to orient the choice of materials to be integrated and their thicknesses to guarantee the integrity of the devices and to optimize the production sequences.

Lors de l'assemblage de wafers par adhésion moléculaire, un mince film d'air est piégé entre les deux wafers, créant ainsi un système fluide/structure couplé.La qualité finale de l'assemblage dépend fortement de la dynamique de ce système.L'initiation et la propagation du collage ont été étudiées, en régime transitoire, en utilisant un modèle de plaques minces couplée avec l'équation de Reynolds. La résolution numérique de l'équation, ainsi que la mesure optique du déplacement vertical de la plaquette durant le collage, nous a permis de valider le modèle et de mieux comprendre la dynamique du collage.Dans la continuité de cette étude, nous avons proposé une expression analytique de la courbure finale de l'assemblage en fonction des forces en jeu pendant le collage, ceci en utilisant à nouveau la théorie des plaques minces et en considérant l'exitence d'un saut de déformation transverse le long de l'interface collée.Ce modèle a été validé par une expérience, impliquant le collage de wafers d'épaisseur différentes et en prenant soin de contrôler l'ensemble des forces agissant sur ces wafers. Nous observons une influence importante du film d'air sur la forme finale des wafers.En complément, un modèle du travail d'adhésion a été développé prenant en compte, à la fois, la rugosité d'interface et la quantité d'eau adsorbée. La différence de répartition de l'eau à l'interface de collage, nous permet d'expliquer les résultats expérimentaux montrant des valeurs d'énergie de séparation supérieure à celle de l'adhésion.Enfin, nous proposons une nouvelle méthode de mesure du travail d'adhésion pour la géométrie entière des wafers, utilisant la mesure de la taille d'une bulle cylindrique intentionnellement créée, par un petit objet, à l'interface de collage. / The direct wafer bonding process involves a coupled physical system, formed by the elastic deformation of the wafers and a thin layer of fluid trapped in-between the two wafers.Dynamics of the system during the contacting step has many practical consequences on the quality of the assembled stack.A model for the bonding dynamics is formulated using the thin plate theory and the Reynolds equation. The transient equation is solved numerically, allowing to study both the initiation and the propagation of the bonding. The model is supported by the measurement of the vertical movement of the wafer during the bonding, using an original setup involving optical sensors.Subsequently, an analytical model for the final curvature of the bonded stack is derived, as a function of the different load components acting on the wafers during the bonding, using the thin plate theory and by considering a transverse strain discontinuity locked at the bonding interface.Experimental validation is performing using two different wafer thicknesses. The measured bonded wafer profiles are well described by the model.In addition, a model for the work of adhesion is developed, taking into account both the interface roughness and the amount of adsorbed water.The interface energy controlling the adhesion is found different than for the separation because of the different distribution of water along the interface, in agreement with the experimental observations. At last, a new method to accurately measure the work of adhesion for the entire wafers geometry is proposed, using an elongated bubble intentionally created at the bonding interface and by measuring the induced wafer deflection.

Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².

A novel CVD copper process is described using two new copper CVD precursors, KI3 and KI5, for the fabrication of IC or TSV (Through Silicon Via) copper interconnects. The highly conformal CVD copper can provide seed layers for subsequent copper electroplating or can be used to directly fabricate the interconnect in one step. These new precursors are thermally stable yet chemically reactive under CVD conditions, growing copper films of exceptionally high purity at high growth rates. Their thermal stability can allow for elevated evaporation temperatures to generate the high precursor vapor pressures needed for deep penetration into high aspect ratio TSV vias. Using formic acid vapor as a reducing gas with KI5, copper films of > 99.99 atomic % purity were grown at 250°C on titanium nitride at a growth rate of > 1500 Å/min. Using tantalum nitride coated TSV type wafers, ~ 1700 Å of highly conformal copper was grown at 225°C into 32 μm × 5 μm trenches with good adhesion. With ruthenium barriers we were able to grow copper at 125°C at a rate of 20 Å/min to give a continuous ~ 300 Å copper film. In this respect, rapid low temperature CVD copper growth offers an alternative to the long cycle times associated with copper ALD which can contribute to copper agglomeration occurring. © 2008 Elsevier B.V.