This dissertation investigates a methodology that can be used to design and optimize an energy efficient 3D-integrated image sensing and compression system for network based applications. A system level model that evaluates the effect of design choices and external environmental factors to the power/performance of the system is presented. Three design principles are considered in formulating the system model. First, a multi-segment/multi-core image compression approach is presented as a combined solution with 3D-stacking to reduce the workload of the compression module, effectively increasing power efficiency of the system. Second, vertical stacking reduces the rate of heat removal from the compression module and ADC resulting in higher temperature and noise in the photodiode tier. Therefore, due to the die-to-die thermal coupling, image quality is strongly influenced by image throughput, architectural, and external environment factors. Third, heterogeneous integration of the photosensor module and compression engine is presented as a method to increase power efficiency of the system. Scaling the compression engine to deep sub-micron technology provides substantial power and chip area benefits, while CMOS image sensor retains reliability with less advanced 180nm process. The dissertation concludes that 3D heterogeneous integration can increase power/performance efficiency of an image sensor system, but die-to-die thermal coupling may provide challenges in managing the quality of the compressed images.

The advent of smart and wearable systems along with their Internet of Things (IoT) applications are driving unparalleled product miniaturization and multifunctional integration with computing, wireless communications, wireless healthcare, security, banking, entertainment, and navigation and others. This evolution is primarily enabled by the integration of multiple technologies such as RF, analog, digital, MEMS, sensors and optics in the same system. Integration of these heterogeneous technologies creates a new need for multiple power supply rails to provide device-specific voltage and current levels. Hence, multiple power converters, each requiring several passive components, are used to create stable power-supplies. However, state-of-art power supplies employ SMD passives that are relatively large, forcing these modules to be placed on the board far from the active IC. This leads to significantly sub-par frequency performance and poses a challenge for ultra-miniaturized and reliable power supplies. Hence, novel packaging technologies that can improve miniaturization, electrical performance and reliability at a relatively low-cost are required to address these challenges. Georgia Tech-PRC proposes 3D integration of passives and actives (3D IPAC) as doubleside thin components on ultra-thin glass substrates with through-package-vias (TPVs) to meet these requirements. This thesis focuses on a comprehensive methodology to demonstrate a 3D IPAC power module, starting with modeling, design, fabrication and characterization to validate 3D integrated ultra-thin inductors and capacitors in ultra-thin substrates. Another key focus of this thesis is to advance building block technologies such as thinfilm inductors and capacitors to achieve the target properties for 3D IPAC integration. As a first building block technology, advanced capacitor technologies were explored with high-k thinfilm barium strontium titanate dielectrics and lanthanum nickel oxide electrodes as an alternative to Cu, Ni and Pt electrodes for improved performance and cost. The BST capacitors with LNO electrodes resulted in a capacitance density of 20-30 nF/cm2 with leakage as low as nA/nF up to 3 V. A glass-compatible process was developed with crystallization temperatures less than 650 C. These capacitors with thinfilm electrodes and dielectrics can be integrated into ultra-thin interposers and packages. This can help improve the capacitor performance up to the GHz range. As a next build block, Si-nanowires were studied as high surface area electrodes for high-density capacitors. Analytical modeling was performed to understand the length of the nanowires based on the catalyst size. This modeling study was then extended to understand the cut-off frequency of the capacitors based on the RC time constant. The wires were fabricated using both chemical vapor deposition (CVD) and wet-etch processes. However, it was noticed that the wet-etch process provided more control on the geometry, density and orientation of the nanowires. Si-oxide was thermally grown on the surface of the wires. A capacitance density of 200 nF/mm2 was achieved. It was noticed that the cut-off frequency of such capacitors was limited to the lower kHz range. However, the operating frequency can be improved by simply using a highly conductive Si-substrate. The second part of the thesis focuses on inductor and capacitor integration on ultra-thin glass substrates for high-frequency power modules using the 3D IPAC approach. Analytical models were used to calculate the required passive component values based on the target frequency, ripple currents and voltages of the power module. Next, a SPICE model was used to optimize the value of the required passives based on the output parasitics. The L and C structures were then modeled using 2.5D method of moments (MOM) approach. The modeling results showed 7-8 X improvement in Q-factor when the structures were fabricated using the 3D IPAC approach relative to those fabricated on the same side of the substrate. A fabrication process flow was designed based on through-via and doubleside metallization with semi-additive patterning (SAP). The components were fabricated as thinfilms on either sides of the substrate and interconnected with through-vias. The LC network was characterized using a two-port vector network analyzer. The results showed low-pass filter response, which matched the design targets of cut-off frequencies upto 100 MHz. This study, therefore, demonstrates advanced thinfilm component technologies for ultra-high frequency power-supply. It also presents, for the first time, a 3D integrated passives and actives (3D IPAC) approach with integrated L and C for power modules.

A high-performance 2D or 3D integrated circuit typically has (i) ratio of delay of a 1mm wire to delay of a nMOS transistor > 500, (ii) target impedence of power delivery network < 1mΩ, (iii) clock frequency > 2GHz, and (iv) thermal resistance requirement of heat removal path < 0.6 degree C/W. This data illustrates the difficulty of obtaining high-quality signal, power, clock and thermal interconnect networks for gigascale 2D and 3D integrated circuits. Specific material, process, circuit, packaging, and architecture solutions to enhance these four types of interconnect networks are proposed and quantitatively evaluated. A microchannel-cooled 3D integrated circuit technology is developed to deal with thermal interconnect problems inherent to stacked dice. The benefits of carbon nanotube technology, improved repeater insertion techniques and parallel processing architectures for signal interconnect networks are evaluated. A circuit technique to periodically reverse current direction in power interconnect networks is proposed. It provides several orders of magnitude improvement in electromigration lifetimes. Methods to control power supply noise and reduce its impact on clock interconnect networks are investigated. Finally, a CAD tool to co-design signal, power, clock and thermal interconnect networks in high-performance 2D and 3D integrated circuits is developed.

Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in laying out flip chip bond pads. Reduction in interconnect parasitics enables these interconnects to support broadband signals, therefore increasing the bandwidth capabilities of flip chip-assembled systems. Traditional flip chip designs provide mechanical and electrical connections from a top chip to a carrier substrate with rigid solder joints. For heterogeneous assemblies, flip chip connections suffer from thermo-mechanical failures caused by coefficient of thermal expansion mismatches. As an alternative, flexible flip chip interconnections incorporating a metal, which is liquid at room temperature, mitigates the possibility of such thermo-mechanical failures. Additionally, liquid metal, flip chip interconnections allow for room temperature assembly, simplifying assembly and rework processes. This dissertation focuses on the design and characterization of liquid metal interconnections, specifically using Galinstan, an alloy of gallium indium and tin, for the heterogeneous assembly of active monolithic microwave integrated circuits (MMICs) onto a CTE mismatched substrate. Carrier substrates designed for liquid metal transitions were fabricated on high resistivity Si and on three dimensional copper structures. The three dimensional copper structures were fabricated in the PolyStrata™ process. Individual MMIC chips were post-processed to mate with carrier substrates in a liquid metal, flip chip configuration. S-parameter measurements of prototype MMIC assemblies with liquid metal, flip chip interconnections showed an average transition loss of 0.7dB over the MMIC's frequency of operation (4.9 - 8.5 GHz). Passive assemblies were also fabricated to characterize the power and temperature performance of liquid metal transitions. Liquid metal interconnections show excellent power handling, maintaining consistent RF performance while transmitting 100W of continuous wave power for an hour. Liquid metal interconnections were also tested following 200 temperature cycles over the -140°C – 125°C range. A comparison of S parameter measurements taken before and after temperature cycling, over a frequency range of 10MHz - 40GHz showed no significant changes in performance. These passive assemblies were also used to develop a lumped element model of the interconnection which is useful for the verification the interconnection\'s performance and for comparison of liquid metal interconnection parasitic to wire bond and flip chip interconnect parasitics. The experimental results presented in this dissertation confirm that liquid metal interconnect are viable for wider use in military and commercial applications. In the future, additional environmental testing and further refinement of the processing flow, such as improved contact metallurgy, are needed to make this interconnect approach more viable for large volume manufacturing. / Ph. D.

In this paper, processing effects of electroplating and post- plating annealing on via extrusion are investigated. The study is based on two TSV structures with identical geometry but different processing conditions. Via extrusion, stress and material behaviors of the TSV structures were first compared. Electron backscatter diffraction (EBSD) and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) were used to characterize the microstructure of TSVs and the additives incorporated during electroplating. Based on the results, processing effects on via extrusion and its mechanism are discussed, including grain growth, local plasticity, and diffusional creep.

Les technologies d'empilement vertical de circuits intégrés, plus connues sous le terme « intégration 3D », ont connu un développement important durant les six dernières années, dans l'optique de proposer une alternative aux approches bidimensionnelles traditionnelles comme les Systems on Chip (SoC). Cette nouvelle architecture a été adaptée au domaine du packaging des circuits intégrés à travers le packaging en 3D réalisé à l'échelle de la plaque ou 3D-WLP pour 3D-Wafer Level Packaging. L'intégration 3D-WLP permet une diminution des tailles des dispositifs finaux, une augmentation de la densité des interconnexions ainsi qu'une réduction des coûts de fabrication. La maîtrise de la réalisation des via traversant, ou TSV pour Through Silicon Via, est une étape clé qui permet d'assurer une connexion électrique entre les différents niveaux empilés. On s'intéresse dans ces travaux de thèse au TSV dans son approche via-last, c'est-à-dire fabriqué en face arrière du dispositif, après les transistors et les niveaux de métallisation de la face avant, et plus particulièrement à l'étape de passivation organique des TSV. En effet, ce via traversant est d'un diamètre trop important pour être complètement rempli avec sa métallisation en cuivre. L'étude concerne donc une solution incluant un remplissage en polymère afin d'améliorer la solution existante en termes de fiabilité et de compatibilité avec des empilements verticaux supplémentaires. / 3D integration technologies for integrated circuits have been widely developed during the six last years in order to propose an alternative to bi-dimensional approaches such as the Systems on Chip (SoC). This new architecture is also used for integrated circuits packaging through 3D-Wafer Level Packaging (3D-WLP). Thus, vertical stacking allows smaller package footprint, higher interconnection density and lower fabrication costs. Through silicon via (TSV) is a key technology that insures vertical electrical interconnection between the stacked levels. This thesis deals with the via-last approach which consists in realizing the TSV at the back-side of the wafer, after the Front End Of the Line (FEOL) and the Back End Of the Line (BEOL), both located at the front-side. During the metallization steps, only a copper liner is electroplated in the TSV since its diameter is too large to achieve a complete metal filling. This study focuses on the TSV polymer insulation step and more specifically, a solution including a TSV polymer filling in order to improve the existing configuration in terms of reliability and compatibility with further 3D stacking.

Les interféromètres de type Mirau sont largement utilisés dans les profilomètres et vibromètres optiques 3D plein champ et d’autres applications dans les domaines de la biologie et de la médecine ont été démontrées. Quand elle a été débutée, cette thèse était la première tentative de réalisation d’interféromètres Mirau entièrement intégrés et accordables en technologie microsystèmes électromécaniques (MEMS) silicium. La conception proposée est fondée sur l’intégration hybride 3D d’un wafer de scanners hors plan de micromiroirs de référence et d’un wafer de séparatrices de faisceaux optiques. La nouveauté majeure de la conception du scanner de miroir est l’utilisation de microactionneurs à peignes électrostatiques verticaux autoalignés réalisés à partir de wafers double Silicium sur Isolant (DSOI). Les modélisations semi-Analytiques et les simulations électromécaniques par éléments finis ont démontré que la combinaison de cet actionnement électrostatique avec des ressorts en serpentins optimisés permet d’obtenir une translation de grande course, bidirectionnelle et symétrique (+/-20µm) du miroir de référence. Un procédé de fabrication original de ce scanner de miroir, reposant largement sur la gravure ionique profonde (DRIE) et des techniques innovantes de délimitation de motifs avec des films secs photosensibles, a été étudié, et les principales étapes critiques de fabrication ont été démontrées avec succès avec des substrats de Si, SOI et DSOI commetciaux. La séparatrice semi-Réfléchissante large bande a été conçue pour être réalisée par une technologie de fabrication de membranes diélectriques multicouches SiO2/SiNx développée précédemment à l’IEF. L’assemblage des wafers de scanners de miroir et de séparatrices sera étudiée dans l’avenir pour obtenir des matrices d’interféromètres Mirau accordables permettant des mesures parallélisées d’interférométrie à décalage de phase ou d’interférométrie faiblement cohérente à balayage dans différentes gammes de longueurs d’onde. / Mirau-Type interferometers are widely used in full field optical 3D profilometers and vibrometers and other applications in biology and medicine fields have been demonstrated. When it was started, this thesis was the first attempt towards the realization of a fully integrated and tunable Mirau interferometer in silicon MEMS technology. The proposed design is based on 3D hybrid integration of an out-Of plane reference micro-Mirror scanner wafer and a optical beam splitter wafer. The major novelty of the micro-Mirror scanner design is the use of self-Aligned vertical electrostatic combs micro-Actuators made from double SOI (DSOI) wafers. Electromechanical modeling by semi-Analytical modeling and finite element simulations demonstrated that the combination of this electrostatic actuation with optimized serpentine suspension springs allows a large range, bidirectional and symmetrical vertical translation (+/-20µm) of the reference mirror. An original fabrication process of this mirror scanner, largely relying on Deep Reactive Ion Etching and on innovative patterning techniques with dry photosensitive films, was investigated, and the main critical fabrication steps were successfully demonstrated with commercial Si, SOI and DSOI substrates. The semi-Reflective broadband beam splitter was designed to be realized by a dielectric SiO2/SiNx multilayer membrane technology previously developed at IEF. Assembly of the mirror scanner and the beam splitter wafers will be investigated in the future to obtain integrated tunable Mirau interferometer arrays allowing parallelized phase shifting interferometry and low coherence scanning interferometry measurements in various wavelength ranges.

The main contribution of this dissertation is the demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, thus reducing delay, power consumption, and area. To adapt planar microarchitectures to 3D-integrated designs, we study several building blocks that together comprise a substantial portion of a processor s total transistor count. In particular, we focus our attention on three basic circuit classes: static random access memory (SRAM) circuits, associative/CAM logic circuits, and data processing in conventional high-performance processors. We propose 2-die-stacked and 4-die-stacked 3D-integrated circuits to deal with the constraints of the conventional planar technology. We propose high-performance 3D-integrated microprocessors and evaluate the impact on performance, power, and temperature. We demonstrate two different approaches to improve performance: clock speed (3D-integrated processors with identical microarchitectural configurations as the corresponding planar processor run at a higher clock frequency), and IPC (3D-integrated processors accommodate larger-sized modules than the planar processors for the same frequency). We demonstrate the simultaneous benefits of the 3D-integration and highlight the power density and thermal issues related to the 3D-integration technology. Next, we propose microarchitectural techniques based on significance partitioning and data-width locality to effectively address the challenges of power density and temperature. We demonstrate that our microarchitecture-level techniques can effectively control the power density issues in the 3D-integrated processors. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power. The simultaneous benefits in multiple objectives make 3D-integration a highly desirable technology for use in building future microprocessors. One of the key contributions of this dissertation is the temperature analysis that shows that the worst-case temperatures on the 3D-integrated processors can be effectively controlled using microarchitecture level techniques. The 3D-integration technology may extend the applicability of Moore s law for a few more technology generations.

As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geometric shrinking, nano patterning with 193nm lithography equipment is one of the most fundamental challenges beyond 22nm while the next-generation lithography, such as Extreme Ultra-Violet (EUV) lithography still faces tremendous challenges for volume production in the near future. As a practical solution, Double Patterning Lithography (DPL) has become a leading candidate for sub-20nm lithography process. Another approach for multi-core integration is 3D wafer stacking with Through Silicon Via (TSV). Computer-Aided-Design (CAD) approaches to enable robust DPL and TSV technology are the main focus of this dissertation. DPL poses new challenges for overlay and layout decomposition. Therefore, overlay induced variation modeling and efficient decomposition for better manufacturability are in great demand. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. Our experiments show that the delay variation due to overlay in DPL can be up to 9.1%, and well decomposed layout can reduce the variability. For DPL layout decomposition, we propose a multi-objective and flexible framework for stitch minimization, balanced density, and overlay compensation, simultaneously. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. Additional decomposition constraints for overlay compensation are obtained by Integer Linear Programming (ILP). Robust contact decomposition can be obtained with additional constraints. With these constraints, global decomposition is performed using a modified Fiduccia-Mattheyses (FM) graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. Three-dimensional integration has new manufacturing and design challenges such as device variation due to TSV induced stress and timing corner mismatch between different stacked dies. Since TSV fill material and silicon have different Coefficients of Thermal Expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. Therefore, the systematic variation due to TSV induced stress should be considered for robust 3D IC design. We propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, a stress contour map with an analytical radial stress model is generated. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relations between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. TSV stress induced timing variations can be as much as 10% for an individual cell. As an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. Three-dimensional Clock Tree Synthesis (3D CTS) is one of the main design difficulties in 3D integration because clock network is spreading over all tiers. In 3D CTS, timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers in 3D CTS. In addition, mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. Therefore, we propose clock period optimization to consider both timing corner mismatch and TSV induced stress. In our experiments, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with the proposed CTS algorithm. As technology scaling continues toward 14nm and 3D-integration, this dissertation addresses several key issues in the design-manufacturing interface, and proposes unified analysis and optimization techniques for effective design and manufacturing integration. / text

The aggressive scaling of the semiconductor technology following the Moore’s Law has delivered true system-on-chip (SoC) integration. Network-on-chip (NoC) has been recently introduced as an effective solution for scalable on-chip communication since dedicated point-to-point (P2P) interconnection and shared bus architecture become performance and power bottlenecks in the SoCs. This dissertation studies three critical NoC challenges such as latency, power, and compatibility with emerging technologies in aspect of an architecture and physical design level. Latency is a key issue in NoC since the performance of applications considerably depends on resource sharing policies employed in an on-chip network. NoCs have been mainly developed to improve network-level performance that captures the inherent performance characteristics of a network itself, but the network-level optimizations are not directly related to application- or system-level performance. In addition, memory latency on NoC critically affects the performance of applications or systems. We propose a synchronous dynamic random access memory (SDRAM) aware NoC design to optimize memory throughput, latency, and design complexity. Furthermore, it is extended to an application-aware NoC design to provide the quality-of-service (QoS) of memory for various applications. NoC provides great on-chip communication. However, it brings no true relief to power budget when the on-chip network scales in terms of complexity/size and signal bandwidth. The combination of NoC and other techniques has the potential to reduce power. We study two power saving research topics for NoC: (a) we propose a voltage-frequency island (VFI) aware NoC optimization framework with a better tradeoff between power efficiency and design complexity to minimize both computation and on-chip communication power. (b) We formulate an application mapping problem to mixed integer quadratic programming (MIQP) with the purpose of reducing power consumption in various hard networks and develop highly efficient algorithms for the MIQP. Regarding NoC compatible with new technologies, we focus on three dimensional (3D) die integration based on through-silicon vias (TSVs). Since an on-chip network design has been subject to not only application constraints but also design/manufacturing constraints, a 3D NoC design is required for innovation in interconnection networks. We propose a chemical-mechanical polishing (CMP) aware application-specific 3D NoC design that minimizes TSV height variation, thus reduces bonding failure, and meanwhile optimizes conventional NoC design objectives such as hop count, wirelength, power, and area. / text