In a typical orthogonal frequency division multiplexing (OFDM) broadband wireless communication system, a guard interval using cyclic prefix is inserted to avoid the inter-symbol interference and the inter-carrier interference. This guard interval is required to be at least equal to, or longer than the maximum channel delay spread. This method is very simple, but it reduces the transmission efficiency. This efficiency is very low in the communication systems, which inhibit a long channel delay spread with a small number of sub-carriers such as the IEEE 802.11a wireless LAN (WLAN). To increase the transmission efficiency, it is usual that a time domain equalizer (TEQ) is included in an OFDM system to shorten the effective channel impulse response within the guard interval. There are many TEQ algorithms developed for the low rate OFDM applications such as asymmetrical digital subscriber line (ADSL). The drawback of these algorithms is a high computational load. Most of the popular TEQ algorithms are not suitable for the IEEE 802.11a system, a high data rate wireless LAN based on the OFDM technique. In this thesis, a TEQ algorithm based on the minimum mean square error criterion is investigated for the high rate IEEE 802.11a system. This algorithm has a comparatively reduced computational complexity for practical use in the high data rate OFDM systems. In forming the model to design the TEQ, a reduced convolution matrix is exploited to lower the computational complexity. Mathematical analysis and simulation results are provided to show the validity and the advantages of the algorithm. In particular, it is shown that a high performance gain at a data rate of 54Mbps can be obtained with a moderate order of TEQ finite impulse response (FIR) filter. The algorithm is implemented in a field programmable gate array (FPGA). The characteristics and regularities between the elements in matrices are further exploited to reduce the hardware complexity in the matrix multiplication implementation. The optimum TEQ coefficients can be found in less than 4µs for the 7th order of the TEQ FIR filter. This time is the interval of an OFDM symbol in the IEEE 802.11a system. To compensate for the effective channel impulse response, a function block of 64-point radix-4 pipeline fast Fourier transform is implemented in FPGA to perform zero forcing equalization in frequency domain. The offsets between the hardware implementations and the mathematical calculations are provided and analyzed. The system performance loss introduced by the hardware implementation is also tested. Hardware implementation output and simulation results verify that the chips function properly and satisfy the requirements of the system running at a data rate of 54 Mbps.

In a typical orthogonal frequency division multiplexing (OFDM) broadband wireless communication system, a guard interval using cyclic prefix is inserted to avoid the inter-symbol interference and the inter-carrier interference. This guard interval is required to be at least equal to, or longer than the maximum channel delay spread. This method is very simple, but it reduces the transmission efficiency. This efficiency is very low in the communication systems, which inhibit a long channel delay spread with a small number of sub-carriers such as the IEEE 802.11a wireless LAN (WLAN). To increase the transmission efficiency, it is usual that a time domain equalizer (TEQ) is included in an OFDM system to shorten the effective channel impulse response within the guard interval. There are many TEQ algorithms developed for the low rate OFDM applications such as asymmetrical digital subscriber line (ADSL). The drawback of these algorithms is a high computational load. Most of the popular TEQ algorithms are not suitable for the IEEE 802.11a system, a high data rate wireless LAN based on the OFDM technique. In this thesis, a TEQ algorithm based on the minimum mean square error criterion is investigated for the high rate IEEE 802.11a system. This algorithm has a comparatively reduced computational complexity for practical use in the high data rate OFDM systems. In forming the model to design the TEQ, a reduced convolution matrix is exploited to lower the computational complexity. Mathematical analysis and simulation results are provided to show the validity and the advantages of the algorithm. In particular, it is shown that a high performance gain at a data rate of 54Mbps can be obtained with a moderate order of TEQ finite impulse response (FIR) filter. The algorithm is implemented in a field programmable gate array (FPGA). The characteristics and regularities between the elements in matrices are further exploited to reduce the hardware complexity in the matrix multiplication implementation. The optimum TEQ coefficients can be found in less than 4µs for the 7th order of the TEQ FIR filter. This time is the interval of an OFDM symbol in the IEEE 802.11a system. To compensate for the effective channel impulse response, a function block of 64-point radix-4 pipeline fast Fourier transform is implemented in FPGA to perform zero forcing equalization in frequency domain. The offsets between the hardware implementations and the mathematical calculations are provided and analyzed. The system performance loss introduced by the hardware implementation is also tested. Hardware implementation output and simulation results verify that the chips function properly and satisfy the requirements of the system running at a data rate of 54 Mbps.

Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. / The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.

Wireless communication is facing one of the fastest developments of the last years in the fields of technology and computer science in the world. There are several standards that deal with it. In this work, the IEEE standard 802.11a, which deals with wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, is going to be discussed in detail. Taking this into consideration, PHY specifications and its environment are going to be studied. The work that the ISY department at the Institute of Technology of the Linköping University has proposed is to design a PHY layer implementation for WLANs, in a CPU, using MATLAB/Simulink and in a DSP processor, using Embedded Target for C6000 DSP and Code Composer Studio and, once implemented both, to perform and analyse the performance of the system under those implementations.

Characteristics of wireless home and office services and the corresponding networking issues are discussed. Local Area Networking (LAN) and Personal Area Networking (PAN) technologies such as IEEE 802.11 and Ultra Wideband (UWB) are introduced. IEEE 802.11a and UWB systems are susceptible to interference from each other due to their overlapping frequencies. The major contribution of this work is to provide a framework for coexistence of the two systems. The interference between the two systems is evaluated theoretically by developing analytical models, and by simulations. It is shown that the interference from UWB on IEEE 802.11a systems is generally insignificant. IEEE 802.11a interference on UWB systems, however, is very critical and can significantly increase the bit error rate (BER) and degrade the throughput of the UWB system. A novel idea in the MAC layer is presented to mitigate this interference by means of temporal separation. Simulation results validate our technique. Implications to wireless home services such as high definition television (HDTV) are provided. Future research directions are discussed.

In the high-speed indoor wireless applications, IEEE 802.11 series is the most dominating LAN standard in the current markets. In this thesis, the design issues of the IEEE 802.11a physical layer baseband system are addressed. Various key modules including Viterbi codec, FFT/IFFT module, OFDM synchronous circuit have been integrated with several other modules to constitute the entire baseband system. This system has been implemented by Verilog HDL and verified against with the C-based behavior model. In addition, it will also be prototyped and optimized on the Altera DSP FPGA Development Board. The transmission of the I, Q channel for the time domain singal is emulated by using the 10-bits AD/DA modules on the FPGA board. The experimental results shows that the gate counts of the transmitter and the receiver are 81,190 and 413,461 respectively.

<p>Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. </p> / <p>The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.</p>

Darbe nagrinėjami bevieliai kompiuteriniai tinklai Wi-Fi ir jų problemos. Nustatomos kelios iš pagrindinių bevielių tinklų problemų. Radijo modulio veikimo režimas yra halfduplex, nepakankamas naudingo srauto perdavimas, srauto klasifikacijos ir prioritetizacijos nebuvimas mano manymu yra pagrindinės bevielio ryšio įrenginių problemos. Bandoma ieškoti problemų sprendimo variantus. Vienas iš galimų sprendimų yra sukurti bevielio ryšio įrenginį, kuris turės šių problemų realizaciją. Ieškoma įrenginiui sukurti būtinų detalių, tokių kaip platforma, radijo modulis, antena ir kitos būtinos detalės. Pirmiausia pasirenkama PC-based platforma dėl to kad turi didesnį produktyvumą ir yra universalesnė. Vienareikšmiškai pasirenkamas 5 GHz radijo dažnis, kadangi įrenginys bus testuojamas ir naudojamas realaus tinklo infrastruktūroje Vilniaus mieste. 2,4 GHz dažnio ruožo naudojimo buvo atsisakyta dėl stipraus užterštumo. Kaip paaiškėjo analizuojamos problemos yra susijusios viena su kita ir reikalauja kompleksinio sprendimo. Buvo nustatyta problemų prigimtis ir jos sprendimas: bendro srauto ribojimas, srautų pagal paskirtį atskyrimas ir jų ribojimas. Ieškomos standartinės ir nestandartinės problemų sprendimo priemonės, tobulinamos, tarpusavyje suderintos ir pritaikytos kuriamai sistemai. Tik realioje tinklo infrastruktūroje su realiais vartotojų generuojamais srautais pavyko nustatyti ir pašalinti trukumus. / This work is an analysis of wireless computer networks Wi-Fi and their problems. Few main wireless networks problems established. Radio module working mode is halfduplex, insufficient transfers of useful data stream, absence of stream classification and prioritisation in my opinion is a main problems of wireless devices. Attempt to search solution of the problems. One of the possible solutions is making an own wireless device witch will have realisation of this problems. Searching for necessary parts to make a device, such as platform, radio module, antenna ant other necessary parts. First of all I have chosen PC-based platform because it has a good productivity ant is more universal. Unambiguous choice was 5 GHz radio frequency, because device will be tested and used in real network infrastructure of Vilnius city. The use of 2,4 GHz radio frequency was rejected because of high radio pollution. It emerged that analysed problems are associated one with another and needs complex solution. Was found nature of this problems and its solutions: total bandwidth shaping, separation of different streams by purpose and their shaping. Searching for standard and nonstandard means to solve such problems, modifying, matching together and adjust to created system. Only in real network infrastructure with real user generated streams was able find and eliminate limitations.

In this thesis, we considered the problem of frame synchronization and channel estimation in Orthogonal Frequency Division Multiplexing (OFDM) systems. Since framing error may cause severe ISI and may disturb the orthogonality of the subcarriers, frame synchronization must be accomplished at the OFDM receiver. Furthermore, the effects of channel must be compensated to obtain the symbols accurately. We investigated several frame synchronization algorithms including a maximum likelihood (ML) synchronizer which relies on the periodicity induced in the OFDM structure, and a robust synchronizer which uses a special training symbol. These algorithms are evaluated in AWGN and Rayleigh fading multipath channels and performances are compared in terms of percentage of ISI-free synchronization, mean squared error and symbol error rate. The IEEE 802.11a framework is used to compare these algorithms with the standard system which utilizes training symbols dedicated for synchronization. It is shown that an adjustment for the frame start estimates must be done to avoid the effects of the channel delay spread. It is also pointed that ideal synchronization is not necessary unless symbol boundaries are detected inside an ISI-free region and the error aroused in ISI-free synchronization can be compensated by applying channel estimation and equalization regarding the same symbol boundaries.

The IEEE 802.11a protocol is part of the IEEE 802 protocols for implementing WLAN Wi- Fi computer communications in various frequencies. These protocols find applications worldwide, covering a wide range of devices like mobile phones, computers, laptops, household appliances, etc. Since wireless communication is being used, data that is transmitted is susceptible to noise. As a means to recover from noise, the data transmitted is encoded using convolutional encoding and correspondingly decoded on the receiver side. The decoder used is the Viterbi decoder, in the PHY layer of the protocol. This thesis investigates soft-decision Viterbi decoder implementations that meet the requirements of the IEEE 802.11a protocol. It aims to implement a rate-flexible design as a coarse grain re-configurable architecture using the SiLago framework. SiLago is a modular approach towards ASIC design. Components are designed as hardened blocks, which means they are synthesised and pre-verified. Each block is also abuttable like LEGO blocks, which allows users to connect compatible blocks and make designs specific to their requirements, while getting performance similar to that of traditional ASICs. This approach significantly reduces the design costs, as verification is a one-time task. The thesis discusses the strongly connected trellis Viterbi decoding algorithm and proposes a design for a soft decision Viterbi decoder. The proposed design meets the throughput requirements of the communication protocol and it can be reconfigured to work for 45 different code rates, with programmable soft decision width and parallelism. The algorithm used is compared against MATLAB for its BER performance. Results from RTL simulations, advantages and disadvantages of the proposed design are discussed. Recommendations for future improvements are also made. / IEEE 802.11a-protokollet är en del av IEEE 802-protokollen för att implementera WLAN Wi-Fi-datorkommunikation i olika frekvenser. Dessa protokoll används i applikationer över hela världen som täcker ett brett spektrum av produkter som mobiltelefoner, datorer, bärbara datorer, hushållsapparater etc. Eftersom trådlös kommunikation används är data som överförs känslig för brus. Som ett medel för att återhämta sig från brus kodas överförd data med hjälp av faltningskodning och avkodas på motsvarande sätt på mottagarsidan. Den avkodare som används är Viterbi-avkodaren, i PHY-skiktet i protokollet. Denna avhandling undersöker mjuka beslut Viterbi avkodarimplementeringar som uppfyller kraven i IEEE 802.11a protokollet. Det syftar till att implementera en hastighetsflexibel design som en grovkornig konfigurerbar arkitektur som använder SiLago ramverket. SiLago är ett modulärt synsätt på ASIC design. Komponenterna är utformade som härda block, vilket innebär att de är syntetiserade och förverifierade. Varje block kan också kopplas ihop, som LEGO block, vilket gör det möjligt för användare att ansluta kompatibla block och göra designer som är specifika för deras krav, samtidigt som de får prestanda som liknar traditionella ASICs. Detta tillvägagångssätt minskar designkostnaderna avsevärt, eftersom verifiering är en engångsuppgift. Avhandlingen diskuterar den starkt kopplade trellis Viterbi-avkodningsalgoritmen och föreslår en design för en mjuk Viterbi-avkodare. Den föreslagna designen uppfyller kommunikationsprotokollets genomströmningskrav och den kan konfigureras om för att fungera för 45 olika kodhastigheter, med programmerbar mjuk beslutsbredd och parallellitet. Algoritmen som används jämförs mot MATLAB för dess BER-prestanda. Resultat från RTL-simuleringar, fördelar och nackdelar med den föreslagna designen diskuteras. Rekommendationer för framtida förbättringar görs också.