Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

This thesis describes theoretic proposal and two practical realization of multi - point wireless network, first for communications between two endpoints and second for wireless signal coverage of a structured space. The wireless network is realized by the equipment working in unlicenced 2,4GHz and 5GHz ISM band. The wireless device are configured in three different wireless mods: WDS, WDS bridge and AP. This paper contains short information about IEEE 802.11a/b/g/n standard and associated proprietary wireless specifications. Practical workshop describes several variants connections and present the result of throughtput measurements, depending on wireless network topology.

A multi-hop ad hoc network requires no infrastructure, like base stations or routers to function. This means that it can quickly be deployed and in movement, making it ideal for scenarios like natural disasters or battlefield communication. A single-frequency network (SFN) is the idea that transmitters can cooperate to send the same signals simultaneously over the same frequency channel, such that the signals are amplified. It was previously proposed that SFNs could be created in multi-hop ad hoc networks. According to simulations, this could improve the energy consumption, signal reachability, and data transfer rate. As this has only been simulated, the purpose of this project is to experimentally verify that SFN is attainable in a multi-hop ad hoc network, and to assess what the difficulties are of an actual implementation. The method involved synchronizing the transmission of two devices operating under the 802.11a standard. A multi-hop ad hoc network was created by changing the settings of the network interface cards. The devices used were mainly laptops and transmissions were monitored in Wireshark. The laptops were forced to send on one frequency channel to make interference possible, and identical packets were sent. Experiments were made to assess whether SFN was attained. The packet loss rate and distance were used to evaluate the results. The results suggest that a synchronized transmission off by less than 2 μs was attained. However, the error of these measurements were neither known nor approximable. This meant it was hard to know when a SFN was formed. The results indicate that SFN was attained, as the packet loss rate decreased significantly when employed. The effectiveness of SFN was hard to assess because the results were not comparable with the simulation values. The difficulty of an actual implementation is deemed to be the synchronization of transmissions.

This thesis describes theoretic proposal and two practical realization of multi - point wireless network, first for communications between two endpoints and second for wireless signal coverage of a structured space. The wireless network is realized by the equipment working in unlicenced 2,4GHz and 5GHz ISM band. The wireless device are configured in three different wireless mods: WDS, WDS bridge and AP. This paper contains short information about IEEE 802.11a/b/g/n standard and associated proprietary wireless specifications. Practical workshop describes several variants connections and present the result of throughtput measurements, depending on wireless network topology.

A new circuit is proposed that uses an RC-CR filter in a feedback configuration to achieve a wideband precision quadrature phase shift with constant amplitude response. Such a circuit can be used to perform image rejection in a low IF receiver using the Hartley method. Simulation results show that the circuit can achieve an average image rejection ratio of 50 dB over a 16 MHz bandwidth. The feedback loop enables the circuit to maintain high accuracy over process and temperature.

With the rapid migration of physical layer design of radio towards software, it becomes necessary to select or develop the platform and tools that help in achieving rapid design and development along with flexibility and reconfigurability. The availability of field programmable gate arrays (FPGAs) has promoted the concept of reconfigurable hardware for software defined radio (SDR). It enables the designer to create high speed radios with flexibility, low latency and high throughput. Generally, the traditional method of designing FPGA based radios limits productivity. Productivity can be improved using Model based design (MBD) tools. These tools encourage a modular way of developing waveforms for radios. The tools based on MBD have been the focus of recent research exploring the concept of the platform independent model (PIM) and portability across platforms by the platform specific model (PSM). The thesis presented here explores the tools based on MBD to achieve prototyping for wireless standards like IEEE 802.11a and IEEE 802.16e on reconfigurable hardware. It also describes the interfacing of the universal software radio peripheral (USRP2), acting as a radio frequency (RF) front end, with an additional FPGA board for baseband processing. / Master of Science

In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit. / Master of Science

In this thesis, we consider an analog antenna combining architecture for a MIMO wireless transceiver, while pointing out its advantages with respect to the traditional MIMO architectures. In the first part of this work, we focus on the transceiver design, especially the calculation of the beamformers that must be applied at the RF. This analysis is performed in an OFDM system under different assumptions on the channel state information. As a result, several criteria and algorithms for the selection of the beamformers are proposed. In the second part, we address the FPGA design and implementation of a baseband processor for this architecture. This baseband processor is based on the standard IEEE 802.11a. Finally, some real-time tests of the implemented baseband processor are carried out both in stand-alone configuration and also with the whole physical layer setup. / En esta tesis consideramos una arquitectura de combinación analógica de antenas para una estación inalámbrica MIMO, señalando las ventajas de ésta con respecto a la arquitectura tradicional MIMO. En la primera parte de este trabajo analizamos el cálculo de los pesos que se deben aplicar en RF. Este análisis es realizado para un sistema OFDM bajo diferentes suposiciones sobre el conocimiento del canal en el transmisor. Como resultado, se ofrecen varios criterios y algoritmos para el cálculo de los pesos. La segunda parte se centra en el diseño y la implementación FPGA de un procesador banda base para esta arquitectura. Este procesador está basando en el estándar IEEE 802.11a. Finalmente se llevan a cabo algunos experimentos en tiempo-real del procesador banda base. Estos experimentos se han realizado tanto con el procesador aislado como integrado en el resto de la capa física del sistema.

The C2X Communication is of high interest to the automotive industry. Ongoing research on this topic mainly bases on the simulation of Vehicular Ad Hoc Networks. In order to estimate the necessary level of simulation details their impact on the results needs to be examined. This thesis focuses on different channel models as the freespace, shadowing, and Ricean model, along with varying parameters. For these simulations the network simulator ns-2 is extended to provide IEEE 802.11p compliance. However, the WAVE mode is not considered since it is still under development and not finally approved. Besides a more sophisticated packet error model than the existing implementation, as well as a link adaptation algorithm, is added. In this thesis several simulations examine specific details of wireless communication systems such as fairness of multiple access, interferences, throughput, and variability. Furthermore, the simulation points out some unexpected phenomena as starving nodes and saturation effects in multi hop networks. Those led to the conclusion that the IEEE 802.11 draft amendment does not solve known problems of the original IEEE 802.11 standard.

<p>Rapporten är en jämförande studie av täckningsgrad och bandbredd i trådlösa nätverk av typ hot-spot med IEEE 802.11A/G respektive IEEE 802.11N Draft 2.0. Studien är gjord i tre olika scenarion på Kvarnholmen i Kalmar under april och maj månad 2008.</p>