Because IC (Integrated Circuit) has some good features like: little, low power consumption, and high stable, so it already popularly applied to our daily life. Operation is one of the main functions of IC, and now operate function achieve in digital mode of many IC products. Although digital circuits have many advantages, but we live in the analog world, natural signals are all analog. Digital circuits can¡¦t direct process analog signals, and therefore we have a requirement of analog-to-digital converter. As time goes by, IC technology has made great progress; digital circuits have faster process ability, and we also require a high speed analog-to-digital converter. Besides, in order to achieve higher picture quality and clearer voice, we also require a high resolution analog-to-digital converter. For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed, high resolution and low power analog-to-digital converter. In this thesis, the circuits are designing with TSMC.18£gm 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit. Keywords: ADC, Analog-to-Digital Converter, pipeline, low power, amplifier, comparator.

The emergence of bandwidth-intensive services has created a need for high speed and high resolution data converters. Towards this end, system level design of a continuous-time sigma-delta modulator achieving 11 bits resolution over 100 MHz signal bandwidth by using a feed-forward topology is presented. The system is first built in the Simulink environment in MATLAB. The building blocks in the loop filter are modeled with non-idealities, and specifications for these blocks are obtained by simulations. An operational transconductor amplifier (OTA) with 100 mS transconductance, 70 dB linearity, and 34.2 mW power dissipation is designed to be used in the loop filter. Simulation results indicate that the 5th order loop filter implemented in the feed-forward architecture in transistor level shows lower power consumption, 105 mW, compared to the loop filter implemented by feedback architecture, 152 mW.

A 2.5V 8-bit 100MSample/sec folding and interpolation analog to digital converter is described in this thesis. First, a cascoding folding amplifier is used for improve power consumption. The differential pairs of the folding amplifier are cascoded to reduce the numbers of reference current source, so the power consumption is reduced. In order to reduce more power consumption, we drop the power supply down to 2.5V. However, the power supply is not large enough to keep the folding amplifier working normally and it causes the output signal aberration. Hence, we propose a back-end amplifier to connect the folding amplifier to overcome the problem. Therefore, the power consumption of all circuit is reduced to 15.292mW. Moreover, the capacitive loading at the output of the cascoded differential pairs is smaller than that of conventional cascaded differential pairs, and we employ a distributed folding technique to reduce the folding factors of each folding amplifier. Therefore, we improve the frequency multiplication effect to increase the analog input signal bandwidth. Beside, in order to heave the input signal range of the voltage mode comparator, we employ an n-channel input stage. Because the input signal range of n-channel is higher than that of p-channel input stage. By using these techniques, the input signal bandwidth and the power consumption of overall circuit are improved greatly. The proposed analog to digital converter is designed by TSMC 0.35£gm 2P4M CMOS process, and it operates at 2.5V power supply voltage with 1V to 2.4V reference voltage. The simulation results show that the power consumption is 15.292mW, DNL is +/- 0.55LSB, and INL is 1.7LSB ~ -0.8LSB.

In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long time operation. As a fundamental building block of ADC, comparator should support a tightened power budget. Therefore, developing low-power design techniques for comparator is becoming more and more important. As an alternative to the conventional voltage-mode comparator, this thesis proposed an energy efficient time-domain comparator, which uses digital circuits to process analog signals by representing them as timing information. The proposed time-domain comparator has three main features: comparing on both clock edges (rising/falling), asynchronous comparison and 2-bit/step comparison. With these features, power consumption of the comparator can be effectively reduced. For verification, the proposed time-domain comparator is fabricated in IBM 0.18um CMOS technology in comparison with other two conventional time-domain comparators working at 100kS/s sampling rate and 8-bit resolution. The achieved power consumption of the proposed time-domain comparator is 50nW, which is much lower than 84nW and 285nW of the other two time-domain comparators.

Error correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. The birth of error correction coding showed that Shannon's channel capacity could be achieved when transmitting information through a noisy channel. Turbo codes are a very powerful form of error correction codes that bring the performance of practical coding even closer to Shannon's theoretical specifications. Bit-error-rate (BER) performance and power dissipation are two important measures of performance used to characterize communication systems. Subject to the law of diminishing returns, as the resolution of the analog-to-digital converter (ADC) in the decoder increases, BER improves, but power dissipation increases. The number of decoding iterations has a similar effect on the BER performance and power dissipation of turbo coded systems. This is significant since turbo decoding is typically practiced in a fixed iterative manner, where all transmitted frames go through the same number of iterations. This is not always necessary since certain "good" frames would converge to their final bits within a few iterations, and other "bad" frames never do converge. In this thesis, we investigate the technical feasibility of adapting the resolution of the ADC in the decoder, and the number of decoding iterations, in order to obtain the best trade-off possible between BER performance and power dissipation in a communication system. With the aid of computer-aided simulations, this thesis investigates the performance and practical implementation issues associated with incorporating a variable resolution ADC into the decoder structure of turbo codes. The possibility of further power conservation resulting from reduced decoding computation is also investigated with the use of a recently developed iterative stopping criterion. / Master of Science

No description available.

Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz. / Master of Science

The objective of this research is to optimize silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS analog circuit building blocks for operation in extreme environments utilizing design techniques. First, negative feedback effects on single-event transient (SET) in SiGe HBT analog circuits were investigated. In order to study the role of internal and external negative feedback effects on SET in circuits, two different types of current mirrors (a basic common-emitter current mirror and a Wilson current mirror) were fabricated using a SiGe HBT BiCMOS technology and exposed to laser-induced single events. The SET measurements were performed at the U.S. Naval Research Laboratory using a two-photon absorption (TPA) pulsed laser. The measured data showed that negative feedback improved SET response in the analog circuits; the highest peak output transient current was reduced by more than 50%, and the settling time of the output current upon a TPA laser strike was shortened with negative feedback. This proven negative feedback radiation hardening technique was applied later in the high-speed 5-bit flash analog-to-digital converter (ADC) for receiver chains of radar systems to improve SET response of the system.

This thesis reports on the design and evaluation of a microprocessor-controlled, high-speed analog-to-digital converter. The processor supervises and manages the digital conversion, split-phase encoding (Manchester) and framing of the input signal. This converter is designed to be applied in an underwater package which will serially transmit sensor data over a fiber optic link to a shore station. This intelligent sensor will provide for ease of future system enhancements. An example would be the implementation of one package to multiplex several analog channels from a local sensor network over the single fiber optic link to the shore station. Keywords: Analog-to-Digital converter, Digital conversion, Split phase encoding, and Manchester. (r.h.) / http://archive.org/details/microprocessorco00schl / U.S. Coast Guard (U.S.C.G.) author.

"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "