The 5G Radio Access Network (RAN) is a critical system that must be secured against potential attacks, particularly its Base-Band Unit (BBU), which is a common target for intrusions. Ericsson, which is a big provider of such systems, has placed significant emphasis on implementing Intrusion Detection Systems (IDS) to detect threats. However, the attention given to Intrusion Response Systems (IRS) in general is limited, with current challenges including false alarms, response cost, response time and reliability. Also, the hardware limitations of the BBU present difficulties in designing an effective IRS. To address these challenges, a semi-automated IRS was implemented with a dynamic and cost-based response selection approach. Open Source SECurity (OSSEC), which is a free, open-source endpoint detection and response tool, was employed to execute the selected responses. The effectiveness of the IRS was assessed based on Ericsson's requirements, reliability, response time, response cost and false alarms. The results obtained show that the proposed IRS is reliable as it can handle a huge number of intrusions and has negligible performance overhead in less extreme attack cases. These findings offer valuable insights into addressing intrusions within a system with constrained hardware resources.

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Current mobile network architecture is facing a big challenge as the traffic demands have been increasing dramatically these years. Explosive mobile data demands are driving a significant growth in energy consumption in mobile networks, as well as the cost and carbon footprints [1]. In 2010, China Mobile Research Institute proposed Cloud Radio Access Network (C-RAN) [2], which has been regarded as one of the most promising architecture to solve the challenge of operators. In C-RAN, the baseband units (BBU) are decoupled from the remote radio units (RRH) and centralized in one or more locations. The feasibility of combination of implementing the very tight radio coordination schemes and sharing baseband processing and cooling system resources proves to be the two main advantages of C-RAN compared to traditional RAN. More importantly, mobile operators can quickly deploy RRHs to expand and make upgrades to their networks. Therefore, the C-RAN has been advocated by both operators and equipment vendors as a means to achieve the significant performance gains required for 5G [3]. However, one of the biggest barriers has shown up in the deployment of C-RAN as the novel architecture imposes very high capacity requirement on the transport network between the RRHs and BBUs, which is been called fronthaul network. With the implementation of 5G wireless system using advanced multi-antenna transmission (MIMO), the capacity requirement would go further up, as well as the power consumption. One solution has been proposed to solve the problem is to have the baseband functions divided, partially staying with RRHs and other functions would be centralized in BBU pool. Different splitting solutions has been proposed in [4] [5] and [6]. In this thesis work, we choose four different splitting solutions to build four CRAN architecture models. Under one specific case scenario with the fixed number of LTE base stations, we calculate the transport capacity requirement for fronthaul and adopt three different fronthaul technology. The power consumption is calculated by adding up the power utilized by RRHs, fronthaul network and baseband processing. By comparing the numerical results, split 1 and 2 shows the best results while split 2 is more practical for dense cell area, since split 1 requires large fronthaul capacity. The fronthaul transport technology can be decided according to different density of base stations. TWDM-PON shows better energy performance as fronthaul network when the capacity requirement is high, compared to EPON. However, for larger number of BSs, mm-Wave fronthaul is a better solution in terms of energy efficiency, fiber saving and flexibility.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / Embedded "Card-Based" receivers are one of the latest innovations in telemetry reception. These products provide substantial power and flexibility in a small form factor (one slot, PC or VME). In many applications they are a cost effective alternative to conventional telemetry receivers. This paper analyzes currently available products with regard to their features, capabilities, and performance, as well as highlighting typical applications.

Thesis (PhD (Electrical and Electronic Engineering)--University of Stellenbosch, 2007. / ENGLISH ABSTRACT: A monostatic baseband radar is required with the capability of detecting close range targets that appear at distances comparable to the system’s resolution, without compromising the radar’s maximum range. The application in borehole radar imposes further constraints associated with the physical limitations and variable electromagnetic environment of different borehole diameters and conditions. This dissertation discusses the complete design process of the analog section of a monostatic radar that successfully addresses these issues. The proposed transceiver employs a series duplexing arrangement consisting of an antenna, transmitter, receiver and an isolation switch. An exponentially decaying tail is observed in the current flowing on a borehole radar antenna when excited by pulse waveforms. The characteristics of this tail depend strongly on the borehole environment. A measurement technique is developed that accurately quantifies this exponential decay by digitizing a logarithmic representation of the antenna current while it is operating in various boreholes. Transmitters are then designed to drive these antennas with waveforms that prevent the formation of current tails. This is achieved through the use of pole-zero networks or alternatively by generating certain asymmetric, bipolar waveforms. The transmitters are simultaneously designed to have an output impedance approximating a short circuit after the transient is generated. In the series configuration proposed here, the duplexing of the antenna between transmitter and receiver is then reduced to simply isolating the receiver during transmit-mode. The switch responsible for this isolation disconnects the receiver and presents a short circuit between antenna and transmitter during transmit-mode, while connecting the receiver terminals between the antenna and the short circuited transmitter terminals in receive-mode. The required close-in performance of the transceiver dictates that the transition between these two states of the isolation switch occur in a time similar to the duration of the transmitter waveform. The switching artefacts generated by the switch are consequently similar to the radar data signal. The isolation switch employs an innovative configuration (using both transistors and diodes) which accepts a single control signal and causes the switching artefacts to be generated as a common mode signal, while a differential path is created for the radar data signal which is being switched. This leads to effective suppression of the switching signal in the signal passed to the receiver. Dissipative filtering is advocated as a fundamental design principle for high fidelity receivers and it is shown how it can be applied by using constant impedance equalizers and diplexers as basic building blocks. This principle is used as the basis for the design of this transceiver's receivers, which incorporate both standard gain blocks and operational amplifiers. A complete borehole radar system, based on the transceiver developed here, was built and tested; resulting in the first known practical monostatic borehole radar system. Data obtained in field trials are presented and suggest that the monostatic system compares well with current state of the art bi-static systems. / AFRIKAANSE OPSOMMING: Die behoefte is geïdentifiseer vir 'n monostatiese basisbandradar wat oor die vermoë beskik om nabygeleë teikens op 'n afstand soortgelyk aan die resolusie van die stelsel waar te neem, sonder om die maksimum bereik van die stelsel in te kort. Die toepassing daarvan in 'n boorgatradarstelsel lei tot verdere vereistes vanweë die fisiese beperkings en veranderende elektromagnetiese omgewing van boorgate met verskillende deursnitte en toestande. Hierdie proefskrif is gemoeid met die volledige ontwerpsprosedure van die analoog gedeelte van 'n monostatiese radar wat al hierdie kwessies aanspreek. 'n Serie verbinding van antenne, sender, ontvanger en isolasieskakelaar word ingespan vir hierdie ontwerp. Eksponensieel wegsterwende stertjies word waargeneem in die antennestroom van 'n boorgatradarantenne wanneer dit aangedryf word deur puls golfvorms. 'n Meettegniek word ontwikkel wat hierdie eksponensiële verslapping noukeurig kan monitor deur 'n logaritmiese voorstelling van die antennastroom te versyfer terwyl dit ontplooi word in verskillende boorgate. Senders word dan ontwikkel om hierdie antennes aan te dryf met golfvorms wat juis die vorming van hierdie stertjies voorkom. Dit word bewerkstellig deur die gebruik van pool-zero netwerke of andersins deur die opwek van sekere asimmetriese, bipolêre golfvorms. Die senders se uittree-impedansies moet egter terselfdertyd ontwerp word om 'n kortsluiting te benader sodra die oorgang klaar opgewek is. Met die serie verbinding wat hier gebruik word, raak die vereiste tyddeling van die antenna tussen die sender en ontvanger dan bloot 'n geval van ontvanger-isolasie gedurende uitsaai-modus. Die skakelaar wat verantwoordelik is vir hierdie isolasie ontkoppel die ontvanger en vertoon soos 'n kortsluiting tussen sender en antenne tydens uitsaai-modus, maar verbind weer die terminale van die ontvanger tussen die antenne en kortgeslote senderterminale tydens ontvang-modus. Die vereiste kortafstand vermoë van die stelsel veroorsaak dat die tysduur van die oorgang tussen hierdie twee modusse soortgelyk is aan dié van die sender golfvorm en enige skakelverskynsels wat opgewek word deur die skakelaar is gevolglik soortgelyk aan die radardatasein self. Die isolasieskakelaar gebruik egter 'n innoverende konfigurasie (met transistors sowel as diodes) wat funksioneer met 'n enkele beheersein en die skakelverskynsels as gemene modus seine opwek, terwyl 'n differensiële seinpad geskep word vir die radardatasein wat geskakel word. Die skakelseine word gevolglik effektief onderdruk in die sein wat oorgedra word aan die ontvanger. Die gebruik van verkwistende filters word voorgestel as 'n fundamentele ontwerpsbeginsel vir hoëtrou ontvangers en daar word getoon hoe dit toegepas kan word met konstante impedansie vereffeningsbane en dipleksers. Hierdie beginsel is dan ook gebruik as basis vir die ontwerp van hierdie stelsel se ontvangers, wat gebruik maak van beide standard aanwinsblokke sowel as operasionel versterkers. 'n Volledige boorgatradarstelsel, gebaseer op die stelsel wat hier ontwikkel is, is gebou en getoets. Die gevolg is die eerste bekende, praktiese monostatiese boorgatradarstelsel. Data wat hiermee verwerf is word aangebied en dui daarop dat die monostatiese stelsel baie goed opweeg teen huidige bi-statiese stelsels.

<p>The advanced signal processing systems of today require extreme data throughput and low power consumption. The only way to accomplish this is to use parallel processor architecture.</p><p>The aim of this thesis was to evaluate the use of parallel processor architecture in baseband signal processing. This has been done by implementing three demanding algorithms in LTE on Ambric Am2000 family Massively Parallel Processor Array (MPPA). The Ambric chip is evaluated in terms of computational performance, efficiency of the development tools, algorithm and I/O mapping.</p><p>Implementations of Matrix Multiplication, FFT and Block Interleaver were performed. The implementation of algorithms shows that high level of parallelism can be achieved in MPPA especially on complex algorithms like FFT and Matrix multiplication. Different mappings of the algorithms are compared to see which best fit the architecture.</p>

The world of wireless communications is under constant change. Radio standards evolve and new standards emerge. More and more functionality is put into wireless terminals. E.g. mobile phones need to handle both second and third generation mobile telephony as well as Bluetooth, and will soon also support wireless LAN functionality, reception of digital audio and video broadcasting, etc. These developments have lead to an increased interest in software defined radio (SDR), i.e. radio devices that can be reconfigured via software. SDR would provide benefits such as low cost for multi-mode devices, reuse of the same hardware in different products, and increased product life time via software updates. One essential part of any software defined radio is a programmable baseband processor that is flexible enough to handle different types of modulation, different channel coding schemes, and different trade-offs between data rate and mobility. So far, programmable baseband solutions have mostly been used in high end systems such as mobile telephony base stations since the cost and power consumption have been considered too high for handheld terminals. In this work a new low power and low silicon area programmable baseband processor architecture aimed for multi-mode terminals is presented. The architecture is based on a customized DSP core and a number of hardware accelerators connected via a configurable network. The architecture offers a good tradeoff between flexibility and performance through an optimized instruction set, efficient hardware acceleration of carefully selected functions, low memory cost, and low control overhead. One main contribution of this work is a study of important issues in programmable baseband processing such as software-hardware partitioning, instruction level acceleration, low power design, and memory issues. Further contributions are a unique optimized instruction set architecture, a unique architecture for efficient integration of hardware accelerators in the processor, and mapping of complete baseband applications to the presented architecture. The architecture has been proven in a manufactured demonstrator chip for wireless LAN applications. Wireless LAN firmware has been developed and run on the chip at full speed. Silicon area and measured power consumption have proven to be similar to that of a non-programmable ASIC solution.

This thesis, for the first time in literature, introduces a comprehensive study about analog controller designs for MEMS vibratory gyroscopes. A controller of a MEMS gyroscope is mandatory for robust operation, which is insensitive to sensor parameters and ambient con- ditions. Errors in the controller design not only deteriorate transient performance, such as settling time and overshoot, but also cause performance degradation due to stability problems. Accordingly, true controller design for a gyroscope is critical work in terms of functionality and system performance. This thesis gives details for modeling, analysis of closed-loop sys- tems, and design procedure for drive and sense modes. Controller loops are implemented both with discrete components and in a CMOS technology as an integrated circuit. Simulation and test results verify the modeling, analysis, and design procedure discussed in this thesis. Drive mode system developed previously at METU is optimized by taking circuit imperfec- tions into account, which results in an improved transient performance of 50 msec settling time with no overshoot for a 4&mu / m drive mode oscillation amplitude. This system has a 60 phase margin with the help of the pole-zero cancellation technique. In addition, a new gener- iv ation and simple drive mode controller for tactical grade applications is designed and verified with a moderate transient performance. Two different sense mode controller design procedures are also developed according to a new base-band equivalent model derived for mismatch operation, as a new contribution to the literature. Firstly, a PID controller is designed for low frequency separation between the drive and sense modes of the gyroscope. Secondly, an integral controller is used for moderate and high mismatch amount. The controller system designed with the new base-band equivalent model improves the linearity, angle random walk, and bias instability by factors of 4, 9, and 3, respectively. Proposed drive and sense mode controllers are also designed and implemented using a 0.6&mu / m standard CMOS process. These chips are the first functional chips developed at METU de- signed for MEMS gyroscopes. Functionality of the proposed three systems, i.e., conventional drive mode controller, new generation drive mode controller, and sense mode controller, are verified with tests. The first prototypes result in 0.033 degree/sqrt/(hr) angle random walk and 3 degree/hr bias instability for open-loop operation, which is very promising and can be improved even further in future designs.

The advanced signal processing systems of today require extreme data throughput and low power consumption. The only way to accomplish this is to use parallel processor architecture. The aim of this thesis was to evaluate the use of parallel processor architecture in baseband signal processing. This has been done by implementing three demanding algorithms in LTE on Ambric Am2000 family Massively Parallel Processor Array (MPPA). The Ambric chip is evaluated in terms of computational performance, efficiency of the development tools, algorithm and I/O mapping. Implementations of Matrix Multiplication, FFT and Block Interleaver were performed. The implementation of algorithms shows that high level of parallelism can be achieved in MPPA especially on complex algorithms like FFT and Matrix multiplication. Different mappings of the algorithms are compared to see which best fit the architecture.

Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems. The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation). High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented. Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers. The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology.