Heterojunction bipolar transistors (HBT) based on SiGeC havebeen investigated. Two high-frequency architectures have beendesigned, fabricated and characterized. Different collectordesigns were applied either by using selective epitaxial growthdoped with phosphorous or by non-selective epitaxial growthdoped with arsenic. Both designs have a non-selectivelydeposited SiGeC base doped with boron and a poly-crystallineemitter doped with phosphorous. Selective epitaxial growth of the collector layer has beendeveloped by using a reduced pressure chemical vapor deposition(RPCVD) technique. The incorporation of phosphorous and defectformation during selective deposition of these layers has beenstudied. A major problem of phosphorous-doping during selectiveepitaxy is segregation. Different methods, e.g. chemical orthermal oxidation, are shown to efficiently remove thesegregated dopants. Chemical-mechanical polishing (CMP) hasalso been used as an alternative to solve this problem. The CMPstep was successfully integrated in the HBT process flow. Epitaxial growth of Si1-x-yGexCy layers for base layerapplications in bipolar transistors has been investigated indetail. The optimization of the growth parameters has beenperformed in order to incorporate carbon substitutionally inthe SiGe matrix without increasing the defect density in theepitaxial layers. The thermal stability of npn SiGe-based heterojunctionstructures has been investigated. The influence of thediffusion of dopants in SiGe or in adjacent layers on thethermal stability of the structure has also been discussed. SiGeC-based transistors with both non-selectively depositedcollector and selectively grown collector have been fabricatedand electrically characterized. The fabricated transistorsexhibit electrostatic current gain values in the range of 1000-2000. The cut-off frequency and maximum oscillation frequencyvary from 40-80 GHz and 15-30 GHz, respectively, depending onthe lateral design. The leakage current was investigated usinga selectively deposited collector design and possible causesfor leakage has been discussed. Solutions for decreasing thejunction leakage are proposed. <b>Key words:</b>Silicon-Germanium-Carbon (SiGeC),Heterojunction bipolar transistor (HBT), chemical vapordeposition (CVD), selective epitaxy, non-selective epitaxy,collector design, high-frequency measurement, dopantsegregation, thermal stability.

Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime silicon wafers for the IC industry. Lately, other substrates, such as silicon-on-insulator has become in use which requires a greater control of the silicon CMP process. CMP is used to planarize oxide interlevel dielectric and to remove excessive tungsten after plug filling in the Al interconnection technology. In Cu interconnection technology, the plugs and wiring are filled in one step and excessive Cu is removed by CMP. In front end processing, CMP is used to realize shallow trench isolation (STI), to planarize trench capacitors in dynamic random access memories (DRAM) and in novel gate concepts. This thesis is focused on CMP for front end processing, which is the processing on the device level and the starting material. The effects of dopants, crystal orientation and process parameters on silicon removal rate are investigated. CMP and silicon wafer bonding is investigated. Also, plasma assisted wafer bonding to form InP MOS structures is investigated. A complexity of using STI in bipolar and BiCMOS processes is the integration of STI with deep trench isolation (DTI). A process module to realize STI/DTI, which introduces a poly CMP step to planarize the deep trench filling, is presented. Another investigated front end application is to remove the overgrowth in selectively epitaxially grown collector for a SiGe heterojunction bipolar transistor. CMP is also investigated for rounding, which could be beneficial for stress reduction or to create microoptical devices, using a pad softer than pads used for planarization. An issue in CMP for planarization is glazing of the pad, which results in a decrease in removal rate. To retain a stable removal rate, the pad needs to be conditioned. This thesis introduces a geometrically defined abrasive surface for pad conditioning.

This work investigates the challenges associated with designing silicon-germanium (SiGe) analog and mixed-signal circuits capable of operating reliably in extreme environment conditions. Three extreme environment operational conditions, namely, operation over an extremely wide temperature range, operation at extremely low temperatures, and operation under radiation exposure, are considered. As a representative for critical analog building blocks, bandgap voltage reference (BGR) circuit is chosen. Several architectures of the BGRs are implemented in two SiGe BiCMOS technology platforms. The effects of wide-temperature operation, deep cryogenic operation, and proton and x-ray irradiation on the performance of BGRs are investigated. The impact of Ge profile shape on BGR's wide-temperature performance is also addressed. Single-event transient response of the BGR circuit is studied through microbeam experiments. In addition, proton radiation response of high-voltage transistors, implemented in a low-voltage SiGe platform, is investigated. A platform consisting of a high-speed comparator, digital-to-analog (DAC) converter, and a high-speed flash analog-to-digital (ADC) converter is designed to facilitate the evaluation of the extreme environment capabilities of SiGe data converters. Room temperature measurement results are presented and predictions on how temperature and radiation will impact their key electrical properties are provided.

No description available.

<p>This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si_1-xGe_x) films for high-speed bipolar transistors.<i>In situ</i>doping of polycrystalline silicon (poly-Si)using phosphine (PH₃) and disilane (Si₂H₆) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H₂desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea.</p><p><b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,<i>in situ</i>doping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect</p>

<p>Heterojunction bipolar transistors (HBT) based on SiGeC havebeen investigated. Two high-frequency architectures have beendesigned, fabricated and characterized. Different collectordesigns were applied either by using selective epitaxial growthdoped with phosphorous or by non-selective epitaxial growthdoped with arsenic. Both designs have a non-selectivelydeposited SiGeC base doped with boron and a poly-crystallineemitter doped with phosphorous.</p><p>Selective epitaxial growth of the collector layer has beendeveloped by using a reduced pressure chemical vapor deposition(RPCVD) technique. The incorporation of phosphorous and defectformation during selective deposition of these layers has beenstudied. A major problem of phosphorous-doping during selectiveepitaxy is segregation. Different methods, e.g. chemical orthermal oxidation, are shown to efficiently remove thesegregated dopants. Chemical-mechanical polishing (CMP) hasalso been used as an alternative to solve this problem. The CMPstep was successfully integrated in the HBT process flow.</p><p>Epitaxial growth of Si1-x-yGexCy layers for base layerapplications in bipolar transistors has been investigated indetail. The optimization of the growth parameters has beenperformed in order to incorporate carbon substitutionally inthe SiGe matrix without increasing the defect density in theepitaxial layers.</p><p>The thermal stability of npn SiGe-based heterojunctionstructures has been investigated. The influence of thediffusion of dopants in SiGe or in adjacent layers on thethermal stability of the structure has also been discussed.</p><p>SiGeC-based transistors with both non-selectively depositedcollector and selectively grown collector have been fabricatedand electrically characterized. The fabricated transistorsexhibit electrostatic current gain values in the range of 1000-2000. The cut-off frequency and maximum oscillation frequencyvary from 40-80 GHz and 15-30 GHz, respectively, depending onthe lateral design. The leakage current was investigated usinga selectively deposited collector design and possible causesfor leakage has been discussed. Solutions for decreasing thejunction leakage are proposed.</p><p><b>Key words:</b>Silicon-Germanium-Carbon (SiGeC),Heterojunction bipolar transistor (HBT), chemical vapordeposition (CVD), selective epitaxy, non-selective epitaxy,collector design, high-frequency measurement, dopantsegregation, thermal stability.</p>

The material and device characteristics of InGaN/GaN heterojunction bipolar transistors (HBTs) grown by metalorganic chemical vapor deposition are examined. Two structures grown on sapphire with different p-InxGa1-xN base-region compositions, xIn = 0.03 and 0.05, are presented in a comparative study. In a second experiment, NpN-GaN/InGaN/GaN HBTs are grown and fabricated on free-standing GaN (FS-GaN) and sapphire substrates to investigate the effect of dislocations on III-nitride HBT epitaxial structures. The performance characteristics of HBTs on FS-GaN with a 20×20 m2 emitter area exhibit a maximum collector-current density of ~12.3 kA/cm2, a D.C. current gain of ~90, and a maximum differential gain of ~120 without surface passivation. For the development of deep-ultraviolet optoelectronics, several various structures of optically-pumped lasers at 257, 246, and 243 nm are demonstrated on (0001) AlN substrates. The threshold-power density at room temperature was reduced to as low as 297 kW/cm2. The dominating polarization was measured to be transverse electric in all cases. InAlN material was developed to provide lattice matched, high-bandgap energy cladding layers for a III-N UV laser structure. This would alleviate strain and dislocation formation in the structure, and also mitigate the polarization charge. However, a gallium auto-doping mechanism was encountered which prevents the growth of pure ternary InAlN, resulting instead in quaternary InAlGaN. This phenomenon is quantitatively examined and its source is explored.

L'analyse et la conception des systèmes en électronique de puissance nécessitent la prise en compte de phénomènes complexes propres à chaque composant du système mais aussi en accord avec son environnement. La description précise du comportement d'un système passe par la simulation utilisant des modèles suffisamment précis de tous ces composants. Dans notre étude, les modèles basés sur la physique des semiconducteurs permettent de décrire le comportement de la charge stockée dans la base large et peu dopée des composants bipolaires. Cette description fine est indispensable à la bonne précision de nos modèles car l'évolution des porteurs dans la base est indissociable du comportement en statique et en dynamique du composant. Ainsi, les modèles physiques analytiques de diode PiN mais surtout d'IGBT NPT ou PT, ayant une technologie de grille 'planar' ou à tranchées sont présentés puis validés. La modélisation de systèmes complexes en électronique de puissance est abordée au travers de deux études. La première concerne l'association des modèles de semiconducteurs avec des modèles de la connectique dans un module de puissance du commerce (3300V /1200A). Une analyse sur les déséquilibres en courant entre les différentes puces en parallèle est donnée. La seconde présente une architecture innovante issue de l'intégration fonctionnelle. Cette architecture faibles pertes permet d'améliorer le compromis chute de tension à l'état passant/ énergie de commutation à l'ouverture inhérent aux composants IGBT. Sa réalisation technologique est présentée au travers de mesure.

The present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX.

Recently, several SiGe HBT devices fabricated on CMOS-compatible silicon on insulator (SOI) substrates (SiGe HBTs-on-SOI) have been demonstrated, combining the well-known SiGe HBT performance with the advantages of SOI substrates. These new devices are especially interesting in the context of extreme environments - highly challenging surroundings that lie outside commercial and even military electronics specifications. However, fabricating HBTs on SOI substrates instead of traditional silicon bulk substrates requires extensive modifications to the structure of the transistors and results in significant trade-offs. The present work investigates, with measurements and TCAD simulations, the performance and reliability of SiGe heterojunction bipolar transistors fabricated on silicon on insulator substrates with respect to operation in extreme environments such as at extremely low or extremely high temperatures or in the presence of radiation (both in terms of total ionizing dose and single effect upset).