Ce document est le résultat de mon travail de thèse au sein du CEA-Leti Grenoble.Il couvre notamment l'évolution de l'effet piézorésistif et des propriétés de transport électrique de transistors à effet de champ en fonction de différentes variables telles que la géométrie, la température, la contrainte mécanique interne....Le point de focalisation de ce travail est d'étudier l'effet de la réduction à l'extrême des dimensions de canal et de grille dans les transistors MOSFET.Une attention spéciale a aussi été portée sur la modélisation des données électriques.Différents algorithmes sont utilisés pour extraire les paramètres clefs des dispositifs, leurs pertinences en fonction des dimensions sont discutées.Un modèle de l'évolution des coefficients piézorésistifs a été dérivé d'un modèle de transport pour les transistors à grilles multiple.Ce modèle permet de prévoir les variations des coefficients piézorésitifs avec la section (largeur et épaisseur du canal) pour un dispositif multigrille.Un effet qui n'est pas prévu par les théories standards pour les dispositifs à très faible section a été montré par les mesures, des hypothèses sont discutées pour expliquer cet effet. / This document is the result of my thesis work at the CEA-Leti Grenoble.It covers the evolution of the piezoresistive effect and the electrical transport properties of field effect transistor device against several variable such as geometry, temperature, internal stress....The focus of this work is to understand the effect brought by extreme reducing of channel and gate dimensions in MOSFET transistors.A special attention is given on electrical data modeling. Different algorithms are used to extract key parameters of devices and their viability against the device dimensions considered is discussed. A new piezoresistive coefficients model is drawn from a known mobility model,it allows to draw a reliable tendancy of piezoresistive variation against the cross section (channel width and thickness) of a given multigate device.An effect not accountable by standard theory for small cross section was shown by the measurements, and some hypothesis are made and discussed to explain whose results.

Il a été démontré que la structure gate-all-around en nanofils de silicium peut radicalement supprimer les effets de canaux courts. De plus, l'introduction d'espaceurs internes entre ces nanofils peut permettre de contrôler la tension de seuil, à l'aide d'une deuxième grille de contrôle. Ces technologies permettent d'obtenir une consommation électrique extrêmement faible. Dans cette thèse, pour obtenir des opérations à haute vitesse (pour augmenter le courant de drain), la technique de réduction de la résistance source/drain sera débattue. Les propriétés de transport électronique des NWs empilées verticalement seront analysées en détail. De plus, des simulations numériques sont effectuées pour examiner les facultés de contrôle de leur tension de seuil utilisant des grilles sépares. / This thesis is titled “A Study on Carrier Transport Properties of Vertically-Stacked Nanowire Transistors,” and is organized in seven chapters in English. 　 Gate-all-around (GAA) silicon nanowire transistors (SNWTs) are one of the best structures to suppress short channel effect for future CMOS devices. In addition, vertically-stacked channel structure benefits from high on-state current owing to reduced footprint. In this thesis, the carrier transport properties of vertically-stacked GAA SNWTs have been experimentally investigated. The vertically-stacked GAA SNWTs were fabricated on SOI wafers by selective etching of SiGe layers in epitaxially-grown Si/SiGe superlattice and top-down CMOS process. The experimental results reveal stacked-channel structure can achieve superior on-state current. It was also found that the effective mobility decreases with diminishing nanowire cross-section width from 30 nm down to 5 nm. This study gives basis and guidelines to optimize the performance of GAA SNWTs for future CMOS devices.

Cette thèse s'inscrit dans le cadre du développement des technologies CMOS 32/28nm chez STMicroelectronics. Elle porte sur l'étude d'empilements de grille métal/diélectrique high-k élaborés selon une stratégie d'intégration Gate First, où le couple TiN/HfSiON est introduit avec une couche interfaciale SiON et une encapsulation de la grille TiN par du polysilicium. Cette étude s'est principalement focalisée sur l'analyse des interactions entre les différentes couches constituant les empilements, en particulier des additifs lanthane et aluminium, employés pour moduler la tension de seuil Vth des transistors NMOS et PMOS respectivement. Les analyses physico-chimiques réalisées au cours de ces travaux ont permis de mettre en évidence la diffusion en profondeur des éléments La et Al à travers le diélectrique de grille HfSiON sous l'effet du recuit d'activation des dopants à 1065°C. Les résultats obtenus ont montré que ce processus de diffusion entraine une réaction du lanthane et de l'aluminium avec la couche interfaciale de SiON pour former un silicate stable La(ou Al)SiO au profit de la couche de SiON. L'analyse des propriétés électrique des structures MOS a permis de révéler que la présence d'atomes La ou Al proximité de l'interface HfSiON/SiON conduit à la présence d'un dipôle généré à cette interface, qui a pour effet de décaler le travail de sortie effectif de la grille métallique. / This thesis is part of the development of CMOS technologies 32/28nm STMicroelectronics. It focuses on the study of stacks of metal / high-k dielectric prepared by an integration strategy Gate First , where the couple TiN / HfSiON gate is introduced with an interfacial layer SiON and encapsulation of TiN gate polysilicon by . The study was mainly focused on the analysis of interactions between the various layers forming the stacks , in particular lanthanum and aluminum additives , used for modulating the threshold voltage Vth of the PMOS and NMOS transistors respectively . The physico-chemical analyzes in this work helped to highlight the depth distribution of the elements La and Al through the HfSiON gate dielectric under the influence of dopant activation annealing at 1065 ° C. The results obtained showed that this diffusion process causes a reaction of lanthanum and aluminum with the interfacial layer of SiON to form a stable silicate La ( or Al ) SiO benefit of the SiON layer . The analysis of electrical properties of MOS structures revealed that the presence of the atoms near the Al or HfSiON / SiON interface leads to the presence of a dipole generated at this interface , which has the effect of shifting actual output work of the metal gate.

Dans le contexte d’une miniaturisation des circuits imprimés dans l’industrie de la microélectronique, les méthodes de structuration optiques appelées photolithographies arrivent en limite de résolution. L’utilisation complémentaire de l’auto-assemblage dirigé (DSA) de copolymère à blocs (CPB) permet de repousser les dimensions critiques (CD) atteignables tout en multipliant la densité des structures obtenues. Ces matériaux peuvent en effet former des motifs géométriques biphasés et périodiques de dimensions inférieures à la vingtaine de nanomètre. Rapides, bas coût et compatibles avec les équipements déjà disponibles dans l’industrie, les différents procédés DSA pour application ligne/espace développés dans la littérature se heurtent néanmoins à des problématiques de défectivité, de rugosité et d’uniformité des dimensions transférées. La plupart des solutions envisagées se font au détriment des arguments de base en faveur du DSA, notamment en ce qui concerne sa compatibilité avec la lithographie actuellement utilisée dans l’industrie. Dans ce contexte, le travail de thèse présenté ici s’attachera à étudier et solutionner les différentes problématiques liées à l’utilisation en graphoépitaxie du DSA comme solution complémentaire à la lithographie conventionnelle. Cette thèse centrée sur le matériau PS-b-PMMA s’est tout d’abord attachée à la compréhension des mécanismes impliqués dans la structuration de ces domaines lamellaires dans deux environnements. En configuration plane tout d’abord, l’impact des paramètres dictant la morphologie, l’orientation et la défectivité du CPB est étudié. La cinétique d’organisation des micro domaines peut alors être optimisée pour obtenir des motifs les mieux définis et les plus stables possibles, en un minimum de temps. Des optimisations matériaux proposées par la société partenaire ARKEMA sont évaluées comme prometteuses, et l’importance du contrôle de l’atmosphère sur le comportement du CPB en température est étudiée. En utilisant ces premiers acquis, le matériau est utilisé pour réaliser la densification de motifs « guides » ligne/espace préalablement réalisés par lithographie optique. L’étude de la morphologie adoptée par le polymère en fonction des multiples paramètres du guide (dimension, chimie d’interface, taux de remplissage…) permet de délimiter des fenêtres de fonctionnement pour un procédé stable sur plaque 300mm. La dimension de ces fenêtres est confirmée par une étude statistique suivant les métriques de défectivité et de rugosité, mesurées par un protocole de métrologie développé pendant cette thèse. Cette première étude a fait l’objet d’une publication d’un papier. Dans un effort de démonstration de l’intérêt de ce procédé, son intégration dans un empilement de réalisation de transistors en nanofils est réalisée. De premiers essais de transfert révèlent des problématiques de défectivités locales jusqu’alors masquées par l’épaisseur du film. Les méthodes de transferts disponibles étant incapables de corriger ces défauts, une variante du procédé DSA est développée. Elle repose sur la possibilité de modifier sélectivement les énergies de surfaces par application d’une dose contrôlée de lumière UV. Une étude associant à la fois la modification de la morphologie du PS-b-PMMA et la composition du matériau (suivie par spectroscopie infrarouge) en fonction de cette dose d’insolation révèle qu’un phénomène de photo-oxydation est responsable de ces phénomènes. Grâce à cette méthode, qui fait l’objet d’une publication en cours de soumission, les surfaces directement en contact avec le CPB sont modifiées de façon à le contraindre à adopter des configurations morphologiques sans défauts enterrés. Ce résultat est confirmé par les différentes étapes de transfert qui permettent de réaliser les nanofils désirés avec des dimensions maîtrisées. Des problématiques d’uniformité de remplissage sont toutefois adressées car elles restent un obstacle des nanofils uniformes à travers une plaque 300mm. / There is a fixed limit to the maximum resolution the photolithography can provide in the context of the integrated circuit’s size reduction encouraged by the microelectronic industry. The Directed Self-Assembly (DSA) of bloc copolymers (BCP) can be used as a complementary technique enabling smaller critical dimensions of features (CD) obtained by density multiplication of initial, loose i193 lithography patterns. These materials can undergo specific phase separation to self-assemble into periodic, sub-20nm ordered nanostructures.Fast, cost-efficient and highly compatible with equipment and techniques already in use in the industry for line/space (L/S) applications, the different DSA processes found in literature still suffer from defectivity, roughness and CD uniformity (CDU) issues. Most successful solutions are made possible at the loss of some of the most appealing DSA features, mainly its compatibility with current i193 lithography. In this context, the work of this thesis studied and proposed innovative solutions to the problematics posed when using graphoepitaxy as the DSA complementary technique.This work presented therein - revolving around a 38nm period lamellar PS-b-PMMA material - first tried to comprehend the mechanisms involved in the self-assembly of lamellae in one of two environment: flat configuration and 3D, graphoepitaxy configuration. In the former, a study of the parameters dictating the morphology, orientation and defect levels of the BCP was performed. This provides a mean to optimize the kinetics of self-assembly to last less than five minutes while enabling stable and reproducible morphology. Materials optimization and atmosphere composition’s impact during annealing is also discussed. This initial knowledge is then used to perform the density multiplication of L/S guiding pattern using conventional optical lithography at Leti. The study of the lamellae morphology as a function of the multiples guiding patterns’ parameters (CD, interface chemistries, thickness levels…) provides fixed process windows (PW) for a stable process over a 300mm wafer. The shape and size of these PWs is further confirmed by a statistic study of defectivity and roughness metrics as defined by a specific metrology protocol developed during this thesis. This work has led to the publication of a paper.In an effort to demonstrate its relevance in the industry, full integration of this DSA process is carried out in pursuit of functional stacked nanowire (NW) transistors acquisition. First etching tests failed though, as they revealed unknown defective formation of the lamellae at the buried interface. The etching process Leti available at Leti proved enable to compensate for these local variations of transfer features. Consequently, a new iteration of the DSA process is presented. It consists in using UV light exposure to selectively shift the interfacial energies of the guiding patterns’ surfaces. A study of the shift in both the observed lamellae morphology and the composition of the material (followed by Infrared Spectroscopy) as a function of the UV dosage is performed. It identifies a photo-oxidation mechanism which can be finely tuned to independently promote defect-free alignment of the BCP lamellae with any of the guiding pattern surfaces. This work, currently awaiting publication, is further verified by the different etching steps achieving monocrystalline silicon nanowires of controlled dimensions. The associated transistors are now being submitted to electrical characterization. Full wafer uniformity of features is a work in progress however, as BCP thickness filling of guiding patterns is still highly dependent on their density.

L’objectif de ces travaux de recherche est la conception en technologie intégrée d’une nouvelle topologie de ligne de transmission accordable afin de réaliser des déphaseurs en bande millimétrique. Cette topologie nommée TS-CPW (pour « Tunable Slow wave CoPlanar Waveguide ») utilise d’une part le phénomène d’ondes lentes qui permet de miniaturiser longitudinalement la ligne de transmission et offre un facteur de qualité plus élevé qu’en technologie microruban intégrée, et d’autre part une approche de type MEMS (Micro Electro Mechanical system) afin obtenir l’accordabilité de la ligne avec une figure de mérite élevée comparativement à une approche de type varactor. Dans un premier temps, la topologie et la conception d’une ligne TS-CPW basée sur des simulations électromagnétiques sont présentées en technologie BiCMOS. Dans un second temps, toujours sur la base de TS-CPWs, des déphaseurs présentant 3-bit de résolution, avec différentes valeurs de déphasage total (de 157.5° et 315°), ont été développés à une fréquence de fonctionnement égale à 60 GHz. Les TS-CPWs et les déphaseurs ont été réalisés avec la technologie BiCMOS 0.25 µm de l’institut IHP en Allemagne, puis mesurés à l’aide d’un analyseur de réseau à IHP et à l’IMEP-LaHc. / This work focuses on the design of millimeter-wave phase shifters based on a new topology of tunable transmission lines named Tunable Slow wave CoPlanar Waveguide (TS-CPW). TS-CPW uses, on one side, the slow wave phenomenon in order to miniaturize longitudinally the transmission line and to show a better quality factor than its integrated microstrip transmission line counterpart and, on the other side, the MEMS approach to achieve tunability of the transmission line with a good figure-of-merit. First, the topology, the design and the electromagnetic simulations of the TS-CPW based on MEMS (Micro Electro Mechanical system) are presented in a BiCMOS technology. Next, phase shifters with 3-bit of resolution based on TS-CPWs are developed at 60 GHz with two different values of total phase shift (157.5° and 315°). These TS-CPWs and phase shifters were fabricated in IHP’s 0.25 µm BiCMOS technology and measured on the vector network analyzers of IHP and IMEP-LaHC.

La réduction continue des dimensions des transistors depuis les années 60 est à l’origine de l’explosion des usages de l’électronique. Toutefois, la réduction des dimensions à l’échelle nanométrique s’accompagne de nouvelles difficultés qui tendent à limiter les gains des transistors en termes de performances et de consommation.Afin de surmonter ces obstacles et maintenir cette dynamique, des canaux à base de nouveaux matériaux à forte mobilité et de nouvelles architectures de transistors sont désormais utilisées ou à l’étude. L’intérêt de films SiGe contraint en compression sur isolant (SGOI: SiGe-On-Insulator) ultra-minces est double : ils bénéficient de la forte mobilité des trous du SiGe contraint en compression ainsi que du meilleur contrôle électrostatique des structures dites « sur isolant ». Des films SGOI présentant une forte concentration en Ge et une importante contrainte peuvent être fabriqués par une technique industrielle appelée condensation. Cette technique repose sur deux processus simultanés : l’oxydation thermique et sélective du SiGe (seul le Si est oxydé) et l’inter-diffusion du SiGe entre l’oxyde thermique et l’oxyde enterré qui se comporte comme une barrière à la diffusion.L’utilisation de cette technique dans un environnement industriel nécessite de relever deux défis : maîtriser les mécanismes et la cinétique d’oxydation, et atteindre les plus fortes contraintes et qualités cristallines pour lesfilms SGOI.La cinétique de plusieurs procédés d’oxydation industriels et pertinents au regard des besoins technologiques actuels est étudiée à l’aide d’une nouvelle méthodologie d’analyse quantitative. Nous établissons une corrélationentre le coefficient de diffusion de l’espèce oxydante, qui détermine la cinétique d’oxydation, la concentration en Ge à l’interface d’oxydation, et la densité de l’oxyde mesurée par réflectivité de rayons X sur une ligne desynchrotron.Puis, nous avons fabriqué des films SGOI présentant des concentrations en Ge jusqu’à 80%. Nous discutons l’évolution de la contrainte de ces films en fonction des paramètres du procédé et des niveaux de contrainte. Enfin,nous mettons en évidence les effets du procédé de condensation sur la qualité cristalline du film SiGe aux interfaces avec les oxydes grâce à l’effet de canalisation d’une technique de rétrodiffusion d’ions à moyenne énergie (MEIS : Medium Energy Ion Scattering) / The tremendous spread of electronic devices and networks into our day-to-day life has been enabled by the constant downscaling of transistors since the 60’s. However, downsizing transistors has become increasingly difficult in the past few years and going to the nanometer scale brings new detrimental effects that have put power consumption and performances on quasi-plateaux for a few years. To overcome these limitations, high mobility channels based on new materials and new transistor architectures are being introduced. Ultrathin compressivelystrained SiGe-On-Insulator (SGOI) films benefit from the advantages of both the higher hole mobility of compressively strained SiGe as well as of the better electrostatic control of On-Insulator structures. The condensation techniqueis a CMOS-compatible technique that allows fabrication of such films with possibly high Ge content and high strain levels. The technique is based on Si-selective thermal oxidation of SiGe and concurrent SiGe diffusion between the thermal oxide and the buried oxide layer that acts as a diffusion barrier.Two main challenges still need to be taken up for an efficient and optimized use of the condensation technique in an industrial environment: oxidation mechanisms and kinetics must be well controlled, and strain and crystal quality of the SGOI film must be as high as possible.Firstly, this work bridges the gap between previous studies by covering various oxidation processes relevant to today’s technological needs with a new and quantitative analysis methodology of oxidation kinetics. A correlation is established between the diffusivity of the oxidizing species that governs oxidation kinetics, the Ge concentration at the oxidation interface, and the oxide density measured by X-Ray Reflectivity on a synchrotron beamline.Secondly, SGOI films with Ge concentrations up to 80% were fabricated by the condensation technique. The evolution of strain of SGOI films is discussed as a function of process parameters and strain energy levels. How the condensation technique alters the crystal quality, both at interfaces with oxides and in the bulk of the SiGe crystal, is evaluated by the Medium Energy Ion Scattering (MEIS) technique by using the channeling effect.

Pas de résumé / CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade. Furthermore technology advancement has provided the capability to integrate more and more functionality into a single chip in multiple layers leading to a new paradigm, 3D integration. CMOS image sensor is one such application which could utilize the capability of 3D stacked architecture to achieve dedicated technologies in different layers, wire length reduction, less area, improved performancesThis research work is focused mainly on the early stages of design space exploration using hierarchical approach and aims at reducing time to market. This work investigates the imager from the top-down design perspective. Methodical anal y sis of imager is performed to achieve high level of flexibility and modularity. Re-useable models are developed to explore early design choices throughout the hierarchy. Finally, pareto front (providing trade off solutions) methodology is applied to explore the operating range of individual block at system level to help the designer making his design choice. Furthermore the thermal issues which get aggravated in the 3D stacked chip on the performance of the imager are studied. Systeme based thermal model is built to investigate the behavior of imager pixel matrix and to simulate the pixel matrix at high speed with acceptable accuracy compared to electrical simulations. The modular nature of the model makes simulations with future matrix extension straightforward. Validation of the thermal model with respect to electrical simulations is discussed. Finally an integrated design flow is developed to perform 3D floorplanning and to perform thermal anal y sis of the imager pixel matrix.

O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura. / The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells. / Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.