This work deals with the two-stage operational amplifier with automatic offset compensation. An operational amplifier is designed in Cadence design environment for possible implementation in technology CMOS07. Emphasis work is placed on minimum offset of the operational amplifier and the parameters, that are listed in the assignment of work.

This thesis focuses on design of an accurate digital to analog converter (DAC). The thesis provides material to understand the principle of conversion of digital signal to analog signal. Some possible structures of DAC are described in this thesis. The selected structure is used for design of the DAC using the CMOS 07 technology. Functionality of the DAC is verified with simulations using the PSPICE simulation program.

Les capteurs d’images cherchent de nos jours non seulement à être performant mais également à être adaptés à leur environnement et à de nouvelles utilisations. On peut évoquer le cas des machines et véhicules autonomes par exemple. En raison de la qualité d’image et son coût, une vaste majorité des applications ont aujourd’hui adopté l’usage des pixels CMOS actifs à photodiodes pincées et à illumination par la face arrière.L’originalité de la solution proposée dans ce manuscrit repose l’intégration d’une photogate, utilisée par les capteurs CCD, au sein d’un pixel CMOS. Son utilisation optimise alors l’espace disponible dans le pixel et diminue le nombre d’implantation nécessaire à sa réalisation. Ce développement a également conduit à l’emploi d’une grille de transfert spécifique. Ces deux nouvelles structures auront toutes les deux été élaborées durant cette thèse notamment à l’aide de simulations et de structures de test.La caractérisation de ce nouveau pixel aura démontré de nombreux atouts : entre autres, l’augmentation de la charge à saturation et la réduction du courant d’obscurité. De plus, l’étude détaillée du courant d’obscurité indique une distribution davantage centrée. Celle-ci permet l’identification de contaminants et une meilleure tenue en température en comparaison à une photodiode classique.De nombreuses perspectives s’offrent à la structure telle que la réduction du pas du pixel ou son utilisation dans un environnement contraint en température. / Nowadays image sensors look neither to be efficient, but rather to be adapted to their environment or to new uses. Autonomous machines and vehicles can be mentioned for instance. Because of image quality and cost, a large majority of applications employs CMOS pixels and pinned back-side illuminated photodiodes.The originality of the solution proposed in this manuscript relies on the integration of a photogate, used by CCD sensors, inside a CMOS pixel. Its use optimize the available space inside the pixel and decrease the number of implantation needed to its realization. This development has also led to the use of specific transfer gate. Both structures have been created during this thesis and designed using simulation and specific test structures.The characterization of the developed pixel demonstrate many assets such as an increase of saturation charges and a reduction of dark current. Furthermore, a detailed study of the dark currant indicates a more gathered pixel distribution, allowing the identification of contaminants and a better temperature handling in comparison to a classical photodiode.The proposed structure offers many perspectives such as reduction of the pixel pitch or its potential use in an environment with a temperature constraint.

No description available.

Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications. However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task. Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals. This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply. In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design. / Master of Science

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.

Color image acquisition and image processing have become a key in modern data application. In order to provide high quality images, the field of accurate acquisition is most important in respect to all further processing steps. But a whole variety of current image sensors possess incorrect color rendition due to insufficient accuracy of optical sensor parameters. This is detrimental especially for color sensors, because in these cases specific color information will be incorrectly acquired. Further, traditional color correction methods do not use information on the specific sensor spectral sensitivity, thus losing substantial information for color correction. The problem is investigated by introducing an algorithmic correction method which is capable of correcting dysfunctional sensor properties. The correction method is based on an enhancement of the CIE color perception model. According to this, color perception is modelled as a special integral transformation, where the spectral sensitivities of the photo receptors represent the base functions of the transformation. It is shown that different sets of photo receptors show the same perception, when their spectral sensitivities are linear dependent. On the other hand, photo receptors with no linear dependency show different perception and there is no analytical transformation between them. Thus, a perfect color correction is only possible if photo sensor and human perception show a linear dependency. In case of dissentient sensor characteristics, the correction method of spectral reconstruction can determine an optimal solution using a least square error optimization. Applying sensors with more than three color channels, this correction method can show improved results due to a better approximation. For implementation of the color correction scheme, different sensor designs have been developed. Compared with currently dominating CCD (Charge Coupled Device) technology, a realisation of image sensors based on CMOS technology show a high potential. CMOS technology allow the integration of the sensor together with control and image processing on the same chip, thus enabling the design of sensor systems at low cost. But modern sub-100nm technologies show also substantial disadvantages, such as increased leakage currents. Special circuit designs have been developed to especially reduce the influence of leakage currents. For application of the color correction method, new multi-channel photo sensors using vertically stacked photo diodes have been developed. The work further shows different concepts of multi-channel sensors capable of high quality color rendition. This approach is demonstrated on several new CMOS sensor designs with examples, implemented in a 90nm Infineon technology.

Le transistor monoélectronique, SET ou single-electron transistor, a été considéré comme étant l’une des alternatives au CMOS lorsqu’il atteindra le « mur technologique ». Le SET se caractérise comme un dispositif ultra faible puissance et nanométrique, mais son faible gain et sa grande dépendance à la température ont fait en sorte que la technologie SET a perdu du momentum vis-à-vis la communauté scientifique. Cependant, en ne considérant pas la technologie SET comme une remplaçante du MOSFET, mais comme quelque chose qui permettrait d’ajouter des fonctionnalités aux circuits CMOS, elle semble être très prometteuse. Cette niche est habituellement appelée l’hybridation SET-CMOS. Ce mémoire débute par une validation des circuits hybrides SET-CMOS présents dans la littérature en remplaçant le modèle de simulation de SET par un modèle beaucoup plus réaliste. De ces circuits hybrides, aucun ne fonctionnera étant donné les courants de fuite trop importants. Le re-design de ces circuits avec ces architectures a été fait avec le bon modèle SET et une technologie CMOS 22 nm, mais leurs performances n’ont pas suffi pour démontrer leur bon fonctionnement (Plage de tension de sortie très faible, aucune bande passante, circuits incomplets, forte dépendance du circuit à ce qui est connecté à la sortie, etc.). Cela a amené à la création de deux nouvelles architectures de circuits de lecture hybrides SET-CMOS. Chaque circuit est conçu avec une technologie CMOS 22 nm. L’une des architectures est principalement adaptée à une application de dispositif capteur SET, où le SET serait éloigné d’un circuit CMOS. Dans l’exemple démontré, le circuit avec le capteur SET donne une sensibilité de 8.4 V par électron peu importe la charge connectée à la sortie du circuit. La nouvelle architecture inventée servirait d’étage tampon entre un circuit numérique fait de SET et un circuit numérique CMOS conventionnel. Dans la littérature, les circuits numériques SET n’ont pas de charge typique lors de leur simulation (ex : un inverseur CMOS), ce qui fausse les résultats en promettant une fréquence haute d’opération impossible à atteindre lors d’une utilisation typique. Ce circuit de lecture numérique fait la lecture du circuit numérique SET, fait le passage entre les deux alimentations différentes et est en mesure de supporter un inverseur CMOS conventionnel à 440 MHz. La consommation de ce circuit n’est que de 5.3 nW lors d’une utilisation à 200 MHz. Cette faible consommation est tout à fait en phase avec l’utilisation de circuits numériques SET qui consomment très peu. Chaque nouvelle architecture inventée a été simulée avec l’ensemble des effets parasites que les interconnexions apportent aux circuits. Les simulations procurent ainsi des résultats plus réalistes. Un procédé de fabrication de circuits hybrides SET-CMOS, où les dispositifs SET sont fabriqués sur le BEOL des puces CMOS avancées, a été développé et testé. Il intègre le procédé nanodamascène, pour la fabrication des nanodispositifs, et la fabrication d’interconnexions/vias afin de relier le CMOS avec les SET. Une démarche pour la validation des dispositifs CMOS a aussi dû être développée et testée. Afin de s’adapter aux dispositifs CMOS à notre disposition, une conception de circuit hybride SET-CMOS a été faite. La fabrication d’un premier prototype recréant un circuit hybride SET-CMOS fût réalisée.

La miniaturisation des technologies Silicium optimise la surface occupée par les supports de télécommunication mobile. La motivation de cette thèse porte sur la conception d'un amplificateur de puissance en technologie CMOS 65 nm qui permet de répondre au standard UMTS W-CDMA. Ce standard exige une grande linéarité et une forte puissance de sortie afin d'assurer une émission à haut débit sur une longue distance. Cette étude porte sur la compatibilité entre la technologie utilisée et les exigences de ce standard."

In this thesis, three broadband low-noise mixing circuits which use CMOS 130 nm technology are presented. As one of the first few stages in a receiving front-end, stringent requirements are posted on mixer performance. The Gilbert cell mixers have presented excellent properties and achieved wide applications. However, the noise of a conventional active Gilbert cell mixer is high. This thesis demonstrates both passive and active mixing circuits with improved noise performance while maintaining the advantages of the Gilbert cell-based mixing core. Furthermore, wide bandwidth and variable gain are implemented, making the designed mixers multi-functional, yet with compact sizes and low power consumptions. The first circuit is a passive 2x subharmonic mixer that works from 4.5 GHz to 8.5 GHz. The subharmonic mixing core is a two-stage passive Gilbert cell driven by a quadrature LO signal. Together with a noise-cancelling transconductor and an inverter-based TIA, this subharmonic mixer possesses an excellent broadband conversion gain and a low noise figure. Measurement results show a high conversion gain of 16 dB and a low average DSB NF of 9 dB. The second design is a broadband low-noise variable gain mixer which operates between 1 and 6 GHz. The transconductor stage is implemented with noise cancellation and current bleeding techniques. Series inductive peaking is used to extend the bandwidth. Gain variation is achieved by a current-steering IF stage. Measurements show a wide gain control range of 13 dB and a low noise performance over the entire frequency and gain range. The lowest DSB NF is 3.8 dB and the highest DSB NF is 14.2 dB. The Third design is a broadband low-noise mixer with linear-in-dB gain control scheme. Using the same transconductance stage with the second circuit, this design also works from 1 to 6 GHz. A 10 dB linear-in-dB gain control range is achieved using an R-r load network with a linear-in-dB error less than $\pm$ 0.5 dB. Low noise performance is achieved. For different frequencies and conversion gains, the lowest DSB NF is 3.8 dB and the highest DSB NF is 12 dB. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-10-02 04:37:31.606