Use of a smartphone as an optical detector for paper microfluidic devices has recently gained substantial attention due to its simplicity, ease of use, and handheld capability. Utilization of a UV light source enhances the optical signal intensities, especially for the particle immunoagglutination assay that has typically used visible or ambient light. Such enhancement is essential for true assimilation of assays to field deployable and point-of-care applications by greatly reducing the effects by independent environmental factors. This work is the first demonstration of using a UV LED (UVA) to enhance the Mie scatter signals from the particle immunoagglutination assay on the paper microfluidic devices and subsequent smartphone detection. Smartphone's CMOS camera can recognize the UVA scatter from the paper microfluidic channels efficiently in its green channel. For an Escherichia coli assay, the normalized signal intensities increased up to 50% from the negative signal with UV LED, compared with the 4% to 7% with ambient light. Detection limit was 10 colony-forming units/mL. Similar results were obtained in the presence of 10% human whole blood.

Doctor of Philosophy / Department of Electrical and Computer Engineering / William B. Kuhn / Design challenges and solution methods for Watt-level UHF CMOS power amplifiers are presented. Using the methods, a fully-integrated UHF (400MHz) CMOS power amplifier (PA) with more than 1-Watt output is demonstrated for the first time in Silicon on Sapphire (SOS) process. The design techniques are extended for a two-stage five-chip 5-Watt CMOS PA. In the 1-Watt PA, a differential stacked PMOS structure with floating-bias and a 1:3 turns-ratio output transformer are chosen to overcome low breakdown voltage (Vbk) of CMOS and chip area consumption issues at UHF frequencies. The high Q on-chip transformer on sapphire substrate enables the differential PA to drive a single-ended antenna effectively at 400 MHz. The PA is designed for a surface-to-orbit proximity link microtransceiver, used on Mars exploration rovers, aerobots and small networked landers. In a standard package the PA delivers 30 dBm output with 27 % PAE. No performance degradation was observed in continuous wave (CW) operation with various output terminations and the PA was tested to 136 % of its nominal 3.3 V supply without failure. Stability analysis and measurements show that the PA is stable in normal operation. It is also shown that the PA is thermally reliable. In the microtransceiver circuits, the PA works in conjunction with transmit/receive (TR) switch to allow nearly the full 1-Watt to reach the antenna. The 1-Watt PA design is also leveraged to demonstrate a power-combined two-stage five-chip PA. The 1-Watt PA’s output balun is modified for the four-transformer combining. Four identical chips are wire-bonded in the output stage and the fifth identical chip is added as a drive-amplifier. Despite low efficiency due to damaged bias circuits, the PA provides 5-Watt output power (37 dBm) at 480 MHz with 17 % PAE with 17 dB gain. The PA layout is carried out considering full integration on a 7×10mm2 die. It will be the highest output CMOS PA ever reported once the full integration is implemented. The research contributes to state of the art by developing design-techniques for a TR switch and PAs on SOS process. The resonant TR switch technique is applied to a full transceiver and the multi turns-ratio on-chip transformer is used in PA’s output matching network for the first time. The PA design is also extended to the 5-Watt PA, demonstrating the highest output power in CMOS process.

Ce travail s’inscrit dans un projet consistant à développer un prototype de capteur RF autonome et intelligent permettant la réalisation d’un réseau de capteurs sans fil dans un environnement industriel. Cette thèse traite de l’étude, la conception et la réalisation de la partie radiofréquence de la chaîne d’émission sans fils du capteur RF dans la bande ISM 863-870 MHz en technologie CMOS AMS 0.35µm. Cette chaîne inclut toutes les fonctions depuis l’oscillateur local jusqu’à l’amplificateur de puissance. L’émetteur occupe une surface de 0.22mm² et consomme environ 27mA sous une tension d’alimentation de 3.3V. De nombreux principes innovants ont été mis en œuvre et validés. Tous ces principes peuvent être facilement transposés à d’autres standards de communication et dans d’autres bandes de fréquences. Les résultats de simulations du dessin des masques vérifient complètement les spécifications et confirment les simulations. Une caractérisation expérimentale partielle valide les nouvelles architectures proposées. / This work joins in a project consisting in developing prototype of an autonomous and smart RF sensor allowing the realization of a wireless sensor network in an industrial environment. This thesis deals with the study, the design and the realization of the radio-frequency part of the transmitter using the 863-870 MHz ISM band and the CMOS AMS 0.35µm technology. This transmitter includes all the functions from the local oscillator to the power amplifier. The integrated circuit occupies a surface of 0.22mm² and consumes approximately 27mA under a supply voltage of 3.3V. Numerous innovative principles were implemented and validated. All these principles can be easily transposed into other standards of communication and in other frequency bands. The results of the post-layout simulation completely satisfy the specifications and confirm the simulations. Partial experimental characterization validates new architectures proposed.

O consumo de energia tem sido uma variável cada vez mais importante nos projetos de implementação de microprocessadores nas últimas décadas. A arquitetura VLIW é um exemplo representativo desta tendência, devido ao seu design simples e desempenho competitivo, resultado da exploração do paralelismo entre instruções (ILP) em tempo de compilação. Neste trabalho, é realizada uma análise da economia de energia obtida através da adaptação da microarquitetura dos processadores VLIW de acordo com as diferentes fases dos programas executados. Primeiramente, o potencial de otimização é abordado, através da execução de um grupo de benchmarks no processador configurável ρ-vex, e estudando o impacto da largura do processador (i.e.: número de issues) na performance, consumo de energia, e área. A partir desta informação, um experimento levando em conta o caso ótimo (usando um oráculo) foi realizado com o objetivo de variar dinamicamente a largura do processador de acordo com a fase do programa, considerando duas granularidades diferentes. A economia de energia usando este tipo de adaptação pode ser de até 81,5% comparado com uma versão estática do mesmo processador executando o grupo de benchmarks MiBench. Com base nestes resultados, duas técnicas de power gating nas unidades funcionais são propostas. A primeira é baseada em lógica adicional, inserida no processador, para controlar os circuitos de power gating associados com cada unidade funcional. Mostra-se que estas unidades podem ser desabilitadas em até 63% do tempo de execução para os multiplicadores e 30% para as ALUs, com um custo em performance de 13%, em média. A segunda técnica proposta propõe uma técnica para ser usada em conjunto com o compilador para aplicar power gating nas unidades funcionais, assim como nos blocos do banco de registradores. Esta operação é realizada inserindo instruções específicas em tempo de compilação, tendo em conta a análise das probabilidades de instruções de saltos e informação dos blocos básicos, obtidos através de instrumentação de código. Utilizando este tipo de estratégia, é possível economizar até 20% em energia com perda marginal de desempenho. / The development of energy efficient hardware has been a trend in microprocessor design for the last two decades. VLIW processors are a representative example, since they have a simpler design and competitive performance, due to their static ILP exploitation. In this work, we study the energy savings that could be obtained by adapting such microarchitecture according to the current program phase. First we analyze the potential of optimization, by executing a set of benchmarks on the ρ-vex configurable softcore VLIW processor, and by modifying the number of issues. With this data in hand, we develop an oracle experiment to dynamically vary the issue width of the processor according to the phase behavior, considering two different phase granularities. The potential energy savings using this policy could be as high as 81.5% when compared with the static version, executing the MiBench set. Taking into account this information, two techniques for power gating the functional units are proposed. The first approach is based on additional hardware logic to control the power gating circuitry of each Functional Unit. Our results show that these units can be put to sleep on average 63% of the execution cycles for the multipliers and 30% for the ALUs, at a performance loss of 13%. The second approach handles intelligent use of the compiler for power gating the Functional Units as well as blocks of the Register File. We do so by inserting customized instructions at compile time, based on the analysis that involves probabilities of conditional branches and basic block information obtained via dynamic profiling. By using this technique, it is possible to save up of 20% in the total energy consumption with marginal losses in performance.

Pour adresser les nœuds technologiques avancés dans le cadre de la lithographie électronique, une nouvelle stratégie de correction des effets de proximité a été imaginée pour prendre le relai de la technique standard de modulation de dose. Dans ces travaux de thèse, les effets de proximité ont été analysés sur les outils e-beam de dernière génération au sein du LETI. Les limites de la modulation de dose ont aussi été évaluées. Parallèlement, une approche plus fondamentale, basée sur la simulation, a permis de mieux comprendre l'impact des différentes étapes du procédé de lithographie sur les motifs réalisés. Une nouvelle stratégie de correction avancée, appelée exposition multiple, a ensuite été mise au point. Celle-ci fait intervenir des motifs spécifiques appelés eRIF (electron Resolution lmprovement Features) dont l'exposition, couplée à celle des motifs initiaux permet de mieux contrôler la répartition de la dose injectée dans la résine. On parle alors d'expositions multiples. Au cours de ces travaux le positionnement des eRIF, ainsi que leurs dimensions ont fait l'objet d'une étude approfondie. L'élaboration d'algorithmes d'optimisation et la réalisation d'expérimentations en salle blanche ont permis d'optimiser ces paramètres et de mettre en évidence les gains apportés par les eRIF. Par rapport à la modulation de dose, des améliorations significatives ont pu être démontrées sur de véritables circuits intégrés. Grâce à l'exposition multiple, la résolution ultime des outils de lithographie e-beam a été repoussée de 2 nœuds technologiques pour les niveaux les plus critiques d'un circuit. Les règles de dessin retenues pour réaliser les eRIF ont ensuite été intégrées dans des modèles de corrections. via le logiciel de préparation de données INSCALE d'ASELTA NANOGRAPHICS pour assurer une correction automatisée des circuits. / In electron beam lithography, a new proximity affects correction strategy has been imagined to push the resolution capabilities beyond the limitations of the standard dose modulation. In this work, the proximity affects inherent to e-beam lithography have been studied on the newest e-beam tools available at LETI. First, the limits of the standard dose modulation correction have been evaluated. The influences of each step of the lithographic process have also been analyzed from a theoretical point a view. A simulation approach was built and used to determine the impact of each of these steps on the patterned features. Then, a new writing strategy has been fully developed. It involves sub resolution features known as eRIF (electron Resolution Improvement features) which provide a finer control of the dose profile into the resist. Since the eRIF are exposed a top the nominal features, this new writing strategy is called multiple pass exposure. In this work, the position, the dose and the design of the eRIF have been studied and optimized to get the best of this new strategy. To do so, experiments were led in a clean room environment, and minimization algorithms have been developed. It has been demonstrated that the eRIF provide a significant gain compared to the standard dose modulation. Improvements have been observed even on the most critical levels of the Integrated circuits. By using the multiple pass exposure with optimized eRIF, the resolution capabilities of the e-beam tool have been reduced by 2 technological nodes. The design rules that have been determined to use the eRIF the most efficient way were finally implemented in INSCALE, the new data preparation software developed by ASELTA NANOGRAPHICS. This way, multiple pass exposure can be used in an automated mode to correct full layouts.

Restoring vision to the blind has been an objective of several research teams for a number of years. It is known that spots of light -- phosphenes -- can be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this, however, our understanding of prosthetic vision remains rudimentary. To advance the realisation of a clinically viable prosthesis for the blind, a versatile integrated circuit neurostimulator was designed, manufactured, and verified. The neurostimulator provides electrical stimuli to surviving neurons in the visual pathway, affording blind patients some form of patterned vision; besides other benefits (independence), this limited vision would let patients distinguish between day and night (resetting their circadian rhythm). This thesis presents the development of the neurostimulator, an interdisciplinary work bridging engineering and medicine. Features of the neurostimulator include: high-voltage CMOS transistors in key circuits, to prevent voltage compliance issues due to an unknown or changing combined tissue and electrode/tissue interface impedance; simultaneous stimulation using current sources and sinks, with return electrodes configured to provide maximum charge containment at each stimulation site; stimuli delivered to a two dimensional mosaic of hexagonally packed electrodes, multiplexing current sources and sinks to allow each electrode in the whole mosaic to become a stimulation site; electrode shorting to remove excess charge accumulated during each stimulation phase. Detailed electrical testing and characterisation verified that the neurostimulator performed as specified, and comparable to, or better than, other vision prostheses neurostimulators. In addition, results from several animal experiments verified that the neurostimulator can elicit electrically evoked visual responses. The features of the neurostimulator enable research into how simultaneous electrical stimulation affects the visual neural pathways; those research results could impact other neural prosthetics research and devices.

Ce mémoire présente une technique de BIST dont l'interface est totalement numérique, pour le test fréquentiel de circuits analogiques et mixtes. L'objectif de cette approche est de faciliter les techniques de test à bas coût des Systèmes sur Puce, rendant le test des blocs mixtes compatibles avec l'utilisation de testeurs numériques. La génération de signal de test analogique est réalisée sur la puce elle-même par un filtrage passe-bas d'un train binaire encodé par un modulateur Sigma-Delta. L'analyse harmonique de la réponse analogique est également réalisée sur la puce en utilisant une modulation par un signal carré et une modulation par un modulateur Sigma-Delta. La génération de signal analogique et l'analyse de la réponse de test étant programmables numériquement sur la puce, la compatibilité avec un testeur numérique à faible coût est assurée. L'optimisation des signatures de test est discutée en détail pour trouver un compromis entre temps et qualité du test.

Les interférences dues à la réseaux d'énergie électrique (50 ou 60 Hz), pendant les mesures de biopotentiels est un problème très commun qui doit être bien tracté, pour permettre l'obtention des résultas en haute qualité. De cette façon les médecin peuvent fournir des diagnostiques plus exact sur le comportement d'une fonction physiologique ou pathologique. Dans les cas où ces signaux sont interprétés à l'aide des systèmes numériques (ordinateurs), c'est très important que les interférences dues à la réseaux électrique soient minimisées pour permettre que points critiques de la forme du signal soient déterminés avec une bonne exactitude. Les circuits mixtes reconfigurables pour des mesures, permettent une nouvelle configuration après la fabrication, de manière qu'ils puissent servir à une application donnée. De cette façon, ces circuits sont convenables pour des applications où ses spécifications doivent changer en accord les capteurs utilisés, e les caractéristiques des signaux sur la mesure. Dans cette thèse un circuit mixte reconfigurable est proposé, pour être utilisé dans des systèmes de mesures des biopotentiels, en particulier électrocardiogramme (ECG), électroencéphalogramme (EEG), électromyogramme (EMG) et électroculogramme (EOG). Le circuit incorpore un bloc qui effectue de forme dynamique la compensation du déséquilibre des impédances des électrodes, de manière à minimiser l'interférence de mode commun, due au couplage entre patient et réseau électrique.

<p>I 0.18 µm CMOS process har ett standardcells bibliotek med låg effektförbrukning implementerats. Cellerna har konstruerats och simulerats i Cadence och ett layoutprogram. Vid simulering av heladderare och D-vippor har effektförbrukningen och tider mätts upp och jämförts med varandra. Matningsspänningen varierade mellan 1 V och 1.8 V. In 0.18 µm CMOS process has a standard cell library with low power consumption been implemented. The cells have been made and simulated in Cadence and a layout program. At the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.</p> / <p>A standard cell library with low power consumption has been implemented in a 0.18 mm CMOS process. The cells have been designed and simulated in Cadence and a layout program. During the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.</p>

<p>This thesis investigates the possibility of realizing bandgap reference crcuits for processes having sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processeshaving near to 1V supply voltage. In the first part of the thesis a comprehensive study on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap reference circuit is designed in the second part of the thesis work. </p><p>The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.</p>