<p>In the European research projects SIAM and 100GET, building blocks for 100Gbit Ethernet optical link have been implemented. Data are sent from a computer, modulated, converted to analog, mixed onto the RF-band, sent through an optical link, down-mixed, converted back to digital, demodulated and sent to a receiving computer. Signal Processing Devices Sweden AB is contributing to this project by their implementation PANDA. This thesis has been to study, as a proof of concept, and implement a prototype of PANDA as the component converting from digital to analog signal, the DAC, in 65nm SOI CMOS technology.</p><p>The idea of the system is to use the concept of time interleaving, where two or more components interact by performing the same operations on a different set of data, ideally scaling the performance linearly with the amount of components used.</p><p>This report presents design, implementation and verification at simulation level. It includes interfacing with off-chip components in low voltage specifications, clock generation, filtering and current-steered switches.</p>

The boom of mobile communications leads to an increasing request of low cost and low power mixed mode integrated circuits. Maturity of SOI technology, and recent progresses of MOSFET's microwave performances, explain the success of silicon as compared to III-V technologies for low-cost multigigahertz analog applications. The design of efficient circuits requires accurate, wide-band models for both active and passive elements. Within this frame, passive components fabricated in SOI technologies have been studied, and a physical model of integrated square spiral inductors has been developed. Also, the performances of integrated MOSFETs have been analyzed. New alternative structures of transistor (the Graded Channel MOSFET and the Dynamic Threshold MOSFET) have been proposed and studied from Low to High frequencies. These transistors show very interesting properties for analog, low power, low voltage, and microwave applications. Furthermore, as their fabrication processes are fully CMOS compatible, they allow us to increase the performances of a CMOS technology without any modification of its process, and without extra-cost.

This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

The boom of mobile communications leads to an increasing request of low cost and low power mixed mode integrated circuits. Maturity of SOI technology, and recent progresses of MOSFET's microwave performances, explain the success of silicon as compared to III-V technologies for low-cost multigigahertz analog applications. The design of efficient circuits requires accurate, wide-band models for both active and passive elements. Within this frame, passive components fabricated in SOI technologies have been studied, and a physical model of integrated square spiral inductors has been developed. Also, the performances of integrated MOSFETs have been analyzed. New alternative structures of transistor (the Graded Channel MOSFET and the Dynamic Threshold MOSFET) have been proposed and studied from Low to High frequencies. These transistors show very interesting properties for analog, low power, low voltage, and microwave applications. Furthermore, as their fabrication processes are fully CMOS compatible, they allow us to increase the performances of a CMOS technology without any modification of its process, and without extra-cost.

Cell detection using image sensors is a novel and promising technique that can be used for diagnostic applications in medicine. For this purpose, cell detection studies with shadowing method are performed with yeast cells (Saccharomyces cerevisiae) using an 32&times / 32 complementary metal oxide semiconductor (CMOS) image sensor that is sensitive to optical illumination. Cells that are placed zero distance from the sensor surface are detected using the image sensor which is illuminated with four fixed leds to maintain fixed illumination levels in each test. Cells are transferred to the sensor surface with drying the medium they are in, which is phosphate buffered saline (PBS) solution. Yeast cells that are zero distance from the surface are detected with a detection rate of 72%. Then, MCF-7 (breast cancer) cells are detected with the same sensor when the PBS solution is about to dry. To investigate the detection capability of the sensor while the cells are in the PBS solution, the sensor surface is coated with gold in order to immobilize the surface with antibodies. With immobilizing antibodies, cells are thought to be bound to the surface achieving zero distance to the sensor surface. After coating gold, antibodies are immobilized, and same tests are done with MCF-7 cells. In the PBS solution, no sufficient results are obtained with the shadowing technique, but sufficient results are obtained when the solution is about to dry. After achieving cell detection with the image sensor, a similar but large format image sensor is designed. The designed CMOS image sensor has 160&times / 128 pixel array with 15&micro / m pitch. The pixel readout allows capacitive and optical detection. Thus, both DNA and cell detection are possible with this image sensor. The rolling line shutter mode is added for reducing further leakage at pixel readout. Addressing can be done which means specific array points can be investigated, and also array format can be changed for different size cells. The frame rate of the sensor can be adjusted allowing the detection of the fast moving cell samples. All the digital inputs of the sensor can be adjusted manually for the sake of flexibility. A large number of cells can be detected with using this image sensor due to its large format.

A 4-PAM/2-PAM receiver analog front-end (AFE) targeting 20GSymbol/s for use with coaxial cable channels is presented. Behavioral simulations incorporate a transmitter, scalable coaxial cable model, and the proposed receiver architecture, targeting cable loss of 32dB at 10GHz. To accommodate links of varying lengths, the AFE includes a variable-gain amplifier (VGA) and analog peaking equalizer. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89mm2 in a 90-nm CMOS process and dissipates 138mW from a 1.3V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s 2-PAM data stream transmitted over coaxial cable with 7.5dB loss at 10GHz.

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

This thesis presents the VLSI implementation and characterization of a 256-channel bidirectional integrated neural interface for adaptive cortical stimulation. The microsystem consists of 64 stimulation and 256 recording channels, implemented in a 0.35um CMOS technology with a cell pitch of 200um and total die size of 3.5mm x3.65mm. The stimulator is a current driver with an output current range of 20uA – 250uA. The current memory in every stimulator allows for simultaneous stimulation on multiple active channels. Circuit reuse in the stimulator and utilization of a single DAC yields a compact and low-power implementation. The recording channel has two stages of signal amplification and conditioning and a single-slope ADC. The measured input-referred noise is 7.99uVrms over a 5kHz bandwidth. The total power consumption is 13.3mW. A new approach to CMOS-microelectrode hybrid integration by on-chip Au multi-stud-bumping is also presented. It is validated by in vitro experimental measurements.

A 4-PAM/2-PAM receiver analog front-end (AFE) targeting 20GSymbol/s for use with coaxial cable channels is presented. Behavioral simulations incorporate a transmitter, scalable coaxial cable model, and the proposed receiver architecture, targeting cable loss of 32dB at 10GHz. To accommodate links of varying lengths, the AFE includes a variable-gain amplifier (VGA) and analog peaking equalizer. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89mm2 in a 90-nm CMOS process and dissipates 138mW from a 1.3V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s 2-PAM data stream transmitted over coaxial cable with 7.5dB loss at 10GHz.

El objetivo de esta tesis es la implementación de sensores de alta resolución, formados por sistemas micro/nano electromecánicos integrados monolíticamente, basados en palanca como elemento transductor y utilizando para la fabricación tecnologías de silicio. En concreto, se determinará la tecnología de fabricación óptima para la implementación de sensores basados en palancas, para aplicaciones en aire o vacio y líquido. Se establecerán las técnicas de detección y excitación adecuadas para los sensores basados en palancas. Y se realiza la compatibilización de la tecnología de fabricación de sensores con la tecnología CMOS, de forma que se consiga la integración monolítica del sistema.Para ello, se fabrican tres demostradores distintos, dos de ellos sensores de masa formados por palancas resonantes y un tercer sistema capaz de trabajar en medio líquido para detección electroquímica. En el primer demostrador se fabrica un sensor de masa formado por una matriz de palancas de polisilicio integrado monolíticamente con la circuitería de lectura. Para ello se utiliza como capa estructural uno de los niveles de polisilicio de la tecnología CMOS utilizada (tecnología CMOS CNM25 2P, 2M con dos niveles de metal y dos niveles de polisilicio). Se han diseñado matrices de cuatro y ocho palancas que permiten realizar medidas multiplexadas de cada una de las palancas independientemente y medidas diferenciales. De forma que por un lado se aumenta la versatilidad del sistema y al realizar medidas diferenciales mejora la resolución. Durante el proceso CMOS se definen las áreas de fabricación y como post-proceso se definen los transductores mecánicos. Tras caracterización eléctrica de los sistemas, de este demostrador se concluye que la integración monolítica es posible y se dispone de un sistema versátil, con resolución en masa inferior a los 40 ag/Hz. El segundo demostrador consiste en un sensor de masa formado por palancas resonantes de silicio cristalino. Para utilizar silicio cristalino como capa estructural se desarrolla una nueva tecnología, a partir de sustratos SOI, que permite definir regiones para fabricación de la circuitería CMOS y regiones con estructura SOI para la implementación de los transductores. Una vez definida la tecnología, se implementan sensores de masa resonantes (como en el primer demostrador) con mejores características de la capa estructural. Se ha probado el funcionamiento de dichos sensores con una resolución máxima en masa de 7 ag/Hz. La tecnología desarrollada permite la fabricación de sistemas MEMS/NEMS integrados monolíticamente que utilizan silicio cristalino como capa estructural. Por ultimo se ha desarrollado un tercer dispositivo, que permite trabajar en medio líquido. Se utiliza como elemento transductor una palanca de silicio cristalino. Para detectar la deflexión de la palanca (provocada por estrés superficial debido al depósito de moléculas) se miden variaciones de corriente electroquímica entre la palanca y un electrodo muy próximo a ella dentro de un bipotenciostato. Es preciso que la separación entre dos electrodos sea inferior a los 100 nm, para poder medir esta corriente. Definir estas separaciones supone un reto tecnológico importante, dado que se trata de definir cortes en silicio de una micra de grosor, con anchura inferior a los 100 nm. Se utilizan técnicas de litografía con resolución nanométrica (con microscopio de fuerzas atómicas, AFM y haz focalizado de iones, FIB) combinadas con grabado seco por iones reactivos (RIE) y ataque directo mediante FIB. Se han conseguido los cortes requeridos y se demuestra el funcionamiento del dispositivo. / The objective of this thesis work is to implement high resolution sensors, formed by micro/nano electromechanical systems integrated monolithically, using cantilevers as transducer and silicon technologies for the fabrication. In particular, the optimal fabrication technology is determined to implement cantilever based sensors for air or vacuum applications and liquid ones. Detection and excitation optimal techniques for cantilever based systems are established. The compatibilization between the sensors fabrication and the CMOS technology is obtained, to achieve the on chip monolithic system.To achieve these objectives, three different demonstrators are fabricated. Two of them are mass sensors formed by resonant cantilevers; the third one is a system able to work in liquid with electrochemical detection. The first demonstrator is a mass sensor formed by a polysilicon cantilevers array integrated monolithically with the readout circuitry. As structural layer, one of the polysilicon layers of the CMOS technology is used (this technology is CMOS CNM25 2P, 2M with two polysilicon layers and to metal ones). Arrays of four and eight cantilevers have been designed, these designs allow multiplexed measures for individual cantilevers and differential measures. On one hand the versatility of the system is increased, by the other differential measures increase the sensor resolution. During CMOS process, fabrication areas are defined; transducers are defined as a post process. After electrical characterization of the system, it can be conclude that the monolithic integration is possible, and it is disposed a versatile system, with mass resolution lower than 40 ag/Hz.A mass sensor formed by resonant cantilevers of crystalline silicon forms the second demonstrator. To use crystalline silicon as structural layer a new technology is developed: from SOI (Silicon on Insulator) substrates, different regions are defined to implement the CMOS on bulk silicon and regions with SOI structure to the transducers. Once, the technology is defined, mass sensors are implemented (like in first demonstrator) increasing the characteristics of the structural layer. IT has been proved the working way of these sensors, with a mass resolution of 7 ag/Hz. The developed technology allows a new platform for MEMS/NEMS fabrications, by monolithic integration and using crystalline silicon as structural layer. Finally, a third device has been defined, which allows to work in liquid. As transducer a crystalline silicon cantilever is used. The deflexion of the cantilever (caused by superficial stress due to molecules adherence) is measured by variations in the electrochemical current between the cantilever and an electrode place close to it, inside a bipotenciostat system. The separation between both electrodes must be smaller than 100nm, to measure this current. The definition of this gaps suppose an important technological issue, due that gaps have to be defined in one micron thick silicon, with a wide smaller than 100 nm. Lithography techniques with nanometric resolutions (atomic force microscope, AFM, and focus ion beam, FIB) combined with reactive ion etching (RIE) are used, together with direct etching with FIB.